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1
An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications by Ouaiss, I.
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2
An automated temporal partitioning tool for a class of DSP applications by Ouaiss, Iyad
Published 1998Other Authors: “…Govindarajan, Sriram…”
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3
An effective design system for dynamically reconfigurable architectures by Ouaiss, I.
Published 2017Other Authors: “…Govindarajan, S.…”
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A unified specification model of concurrency and coordination for synthesis from VHDL by Ouaiss, Iyad
Published 2017Other Authors: “…Govindarajan, Sriram…”
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5
An integrated partitioning and synthesis system for dynamically reconfigurable Multi-FPGA architectures by Ouaiss, Iyad
Published 2017Other Authors: “…Govindarajan, Sriram…”
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