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  1. 1
    A method for optimizing test bus assignment and sizing for system-on-a-chip

    A method for optimizing test bus assignment and sizing for system-on-a-chip by Harmanani, Haidar M.

    Published 2017
    Other Authors: “…Sawan, Rachel…”
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  2. 2
    Test bus assignment, sizing, and partitioning for system-on-chip

    Test bus assignment, sizing, and partitioning for system-on-chip by Harmanani, Haidar M.

    Published 2007
    Other Authors: “…Sawan, Rachel…”
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  3. 3
    Test time minimization for system-on-chip with test bus assignment and sizin

    Test time minimization for system-on-chip with test bus assignment and sizin by Harmanani, Haidar M.

    Published 2017
    Other Authors: “…Sawan, Rachel…”
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