Energy-Aware Physical Synthesis of Deep Neural Networks for Edge-AI Applications in Robotics and VLSI Systems
Energy-aware physical synthesis is essential for deploying deep neural networks (DNNs) in edge-AI applications for robotics and VLSI systems, where stringent power, area, and latency constraints prevail. Beyond algorithm-and software-level optimizations such as network compression and compiler techn...
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| مؤلفون آخرون: | , , , , , |
| التنسيق: | article |
| منشور في: |
2025
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| الوصول للمادة أونلاين: | http://hdl.handle.net/11675/14472 https: |
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| _version_ | 1870679729404641281 |
|---|---|
| author | Arulprakash, Enoch |
| author2 | Bostani, Ali Jayanthi, R. Kowsalya, G. Ramalingam, M. Rathi, M. Srilatha, Y. |
| author2_role | author author author author author author |
| author_facet | Arulprakash, Enoch Bostani, Ali Jayanthi, R. Kowsalya, G. Ramalingam, M. Rathi, M. Srilatha, Y. |
| author_role | author |
| dc.creator.none.fl_str_mv | Arulprakash, Enoch Bostani, Ali Jayanthi, R. Kowsalya, G. Ramalingam, M. Rathi, M. Srilatha, Y. |
| dc.date.none.fl_str_mv | 2025-01-20 2026-06-03T10:09:31Z 2026-06-03T10:09:31Z |
| dc.identifier.none.fl_str_mv | 10.31838/JVCS/07.01.23 http://hdl.handle.net/11675/14472 https: www.scopus.com/pages/publications/105020281769 |
| dc.publisher.none.fl_str_mv | Society for Communication and Computer Technologies |
| dc.relation.none.fl_str_mv | Electrical and Computer Engineering Journal of VLSI Circuits and Systems |
| dc.title.none.fl_str_mv | Energy-Aware Physical Synthesis of Deep Neural Networks for Edge-AI Applications in Robotics and VLSI Systems |
| dc.type.none.fl_str_mv | Article info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | Energy-aware physical synthesis is essential for deploying deep neural networks (DNNs) in edge-AI applications for robotics and VLSI systems, where stringent power, area, and latency constraints prevail. Beyond algorithm-and software-level optimizations such as network compression and compiler techniques, the physical effects during VLSI imple-mentation including clock tree synthesis (CTS), routing congestion, IR-drop, cell sizing, and placement significantly influence energy consumption and timing closure. This work presents a unified framework that co-optimizes DNN architectural features (including quantization, sparsity, and operator tiling) with physical design choices, such as multi-Vt selection, sizing, placement strategies, activity-driven buffering, and CTS. The proposed methodology formulates a multi-objective optimization targeting minimum energy at iso-throughput, meeting timing and area constraints via analytic models and sign-off cali-brated power estimates. A co-design loop iteratively reshapes the network and refines physical synthesis using sensitivity to activity factors and critical-path slack. The framework is validated with prototype RTL for representative CNN/transformer blocks, imple-mented on open PDKs and evaluated on FPGA/SoC testbeds for mobile robotics scenarios. Results demonstrate 28–41% reduction in energy per inference under constant accuracy and throughput, 12–18% lower leakage with multi-Vt and sizing, and a 1.6× improvement in worst-negative-slack closure probability across 500–800 MHz operation. Ablation stud-ies clarify the impact of quantization-aware placement and activity-weighted CTS. The framework integrates seamlessly with standard EDA flows and IEEE design rules, enabling automated hardware-software co-optimization for practical edge-AI deployments. |
| format | article |
| id | AUKR_08a02dbff6433fa53a009c32b0fc8287 |
| identifier_str_mv | 10.31838/JVCS/07.01.23 www.scopus.com/pages/publications/105020281769 |
| network_acronym_str | AUKR |
| network_name_str | AU Kuwait Rep |
| oai_identifier_str | oai:dspace.auk.edu.kw:11675/14472 |
| publishDate | 2025 |
| publisher.none.fl_str_mv | Society for Communication and Computer Technologies |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | Energy-Aware Physical Synthesis of Deep Neural Networks for Edge-AI Applications in Robotics and VLSI SystemsArulprakash, EnochBostani, AliJayanthi, R.Kowsalya, G.Ramalingam, M.Rathi, M.Srilatha, Y.Energy-aware physical synthesis is essential for deploying deep neural networks (DNNs) in edge-AI applications for robotics and VLSI systems, where stringent power, area, and latency constraints prevail. Beyond algorithm-and software-level optimizations such as network compression and compiler techniques, the physical effects during VLSI imple-mentation including clock tree synthesis (CTS), routing congestion, IR-drop, cell sizing, and placement significantly influence energy consumption and timing closure. This work presents a unified framework that co-optimizes DNN architectural features (including quantization, sparsity, and operator tiling) with physical design choices, such as multi-Vt selection, sizing, placement strategies, activity-driven buffering, and CTS. The proposed methodology formulates a multi-objective optimization targeting minimum energy at iso-throughput, meeting timing and area constraints via analytic models and sign-off cali-brated power estimates. A co-design loop iteratively reshapes the network and refines physical synthesis using sensitivity to activity factors and critical-path slack. The framework is validated with prototype RTL for representative CNN/transformer blocks, imple-mented on open PDKs and evaluated on FPGA/SoC testbeds for mobile robotics scenarios. Results demonstrate 28–41% reduction in energy per inference under constant accuracy and throughput, 12–18% lower leakage with multi-Vt and sizing, and a 1.6× improvement in worst-negative-slack closure probability across 500–800 MHz operation. Ablation stud-ies clarify the impact of quantization-aware placement and activity-weighted CTS. The framework integrates seamlessly with standard EDA flows and IEEE design rules, enabling automated hardware-software co-optimization for practical edge-AI deployments.Society for Communication and Computer Technologies2026-06-03T10:09:31Z2026-06-03T10:09:31Z2025-01-20Articleinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/article10.31838/JVCS/07.01.23http://hdl.handle.net/11675/14472https:www.scopus.com/pages/publications/105020281769Electrical and Computer EngineeringJournal of VLSI Circuits and Systemsoai:dspace.auk.edu.kw:11675/144722026-06-03T12:38:03Z |
| spellingShingle | Energy-Aware Physical Synthesis of Deep Neural Networks for Edge-AI Applications in Robotics and VLSI Systems Arulprakash, Enoch |
| status_str | publishedVersion |
| title | Energy-Aware Physical Synthesis of Deep Neural Networks for Edge-AI Applications in Robotics and VLSI Systems |
| title_full | Energy-Aware Physical Synthesis of Deep Neural Networks for Edge-AI Applications in Robotics and VLSI Systems |
| title_fullStr | Energy-Aware Physical Synthesis of Deep Neural Networks for Edge-AI Applications in Robotics and VLSI Systems |
| title_full_unstemmed | Energy-Aware Physical Synthesis of Deep Neural Networks for Edge-AI Applications in Robotics and VLSI Systems |
| title_short | Energy-Aware Physical Synthesis of Deep Neural Networks for Edge-AI Applications in Robotics and VLSI Systems |
| title_sort | Energy-Aware Physical Synthesis of Deep Neural Networks for Edge-AI Applications in Robotics and VLSI Systems |
| url | http://hdl.handle.net/11675/14472 https: |