Digital Logic Design
محفوظ في:
| المؤلف الرئيسي: | |
|---|---|
| منشور في: |
2018
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| الوصول للمادة أونلاين: | http://hdl.handle.net/11675/3305 |
| الوسوم: |
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| _version_ | 1870679726160347136 |
|---|---|
| author | Khanafer, Mounib |
| author_facet | Khanafer, Mounib |
| author_role | author |
| dc.contributor.none.fl_str_mv | College of Arts and Sciences |
| dc.creator.none.fl_str_mv | Khanafer, Mounib |
| dc.date.none.fl_str_mv | 2018-06-01T12:39:54Z 2018-06-01T12:39:54Z 2018 |
| dc.format.none.fl_str_mv | application/pdf |
| dc.identifier.none.fl_str_mv | CPEG 210 http://hdl.handle.net/11675/3305 |
| dc.language.none.fl_str_mv | en_US |
| dc.publisher.none.fl_str_mv | Electrical and Computer Engineering |
| dc.relation.none.fl_str_mv | Section 2 & 3 Digital Design with an introduction to VHDL, |
| dc.title.none.fl_str_mv | Digital Logic Design |
| dc.type.none.fl_str_mv | Syllabus info:eu-repo/semantics/publishedVersion |
| id | AUKR_ed2d3412b032d2cfe0795c77f073ff95 |
| identifier_str_mv | CPEG 210 |
| language_invalid_str_mv | en_US |
| network_acronym_str | AUKR |
| network_name_str | AU Kuwait Rep |
| oai_identifier_str | oai:dspace.auk.edu.kw:11675/3305 |
| publishDate | 2018 |
| publisher.none.fl_str_mv | Electrical and Computer Engineering |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | Digital Logic DesignKhanafer, MounibElectrical and Computer EngineeringCollege of Arts and Sciences2018-06-01T12:39:54Z2018-06-01T12:39:54Z2018Syllabusinfo:eu-repo/semantics/publishedVersionapplication/pdfCPEG 210http://hdl.handle.net/11675/3305en_USSection 2 & 3Digital Design with an introduction to VHDL,oai:dspace.auk.edu.kw:11675/33052022-01-12T06:06:46Z |
| spellingShingle | Digital Logic Design Khanafer, Mounib |
| status_str | publishedVersion |
| title | Digital Logic Design |
| title_full | Digital Logic Design |
| title_fullStr | Digital Logic Design |
| title_full_unstemmed | Digital Logic Design |
| title_short | Digital Logic Design |
| title_sort | Digital Logic Design |
| url | http://hdl.handle.net/11675/3305 |