A Hybrid Test Compression Technique for Efficient Testing of Systems-on-a-Chip
One of the major challenges in testing a System-on-a-Chip (SOC) is dealing with the large test data size. To reduce the volume of test data, several efficient test data compression techniques have been recently proposed. In this paper, we propose hybrid test compression techniques that combine the G...
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| Format: | article |
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2003
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/160/1/hybrid_compression_icecs2003.pdf |
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