Khan, F., & unknown. (2009). Transistor-Level Defect-Tolerant Techniques for Reliable Design at the Nanoscale.
Chicago Style (17th ed.) CitationKhan, Farhan, and unknown. Transistor-Level Defect-Tolerant Techniques for Reliable Design at the Nanoscale. 2009.
MLA (9th ed.) CitationKhan, Farhan, and unknown. Transistor-Level Defect-Tolerant Techniques for Reliable Design at the Nanoscale. 2009.
Warning: These citations may not always be 100% accurate.