Efficient test relaxation techniques for combinational logic circuits

Efficient test relaxation techniques for combinational logic circuits

محفوظ في:

التفاصيل البيبلوغرافية
المؤلف الرئيسي:	Al-Suwaiyan, Ali Saleh Mohammed (author)
مؤلفون آخرون:	unknown (author)
التنسيق:	masterThesis
منشور في:	2002
الموضوعات:	Computer
الوصول للمادة أونلاين:	https://eprints.kfupm.edu.sa/id/eprint/10403/1/10403.pdf
الوسوم:	إضافة وسم لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!

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