HARDWARE DESIGN AND VLSI IMPLEMENTATION OF A BYTE-WISE CRC GENERATOR CHIP
In this paper the ahrdware design and VLSi implementation of a byte-wise CRC generator is presented. The algorithm is based on the work presented in [10] in which a software implementation was proposed. The byte-wise CRC algorithm is translated to hardware and expressed in AHPL [6]. The method used...
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| Format: | article |
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2020
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/294/1/J_Sait_CE_February1995.pdf |
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| Summary: | In this paper the ahrdware design and VLSi implementation of a byte-wise CRC generator is presented. The algorithm is based on the work presented in [10] in which a software implementation was proposed. The byte-wise CRC algorithm is translated to hardware and expressed in AHPL [6]. The method used here calculates CRC on the fly and is muc faster than the look-up table method proposed by Lee[5]. The chip is 8 times faster that the serial implementation of [12] with smaller hardware requirements (occupies lesser area). The number of clocl cycles required to generate and transmitany CRC (for an 8 hour bytemessage) is just two more that the time required to calculate it (in all 10 clocl pulses. The CRC chip can be used in anumber of applications. These include areas such as error detection and correction in data comunication, signature analysis and mass storage devices for parallel information transfers. |
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