A static test compaction technique for combinational circuits based on independent fault clustering
Testing system-on-chip involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in...
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| Format: | article |
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2003
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14098/1/14098_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14098/2/14098_2.doc |
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| _version_ | 1864513393348575232 |
|---|---|
| author | Osais, Y.E. |
| author2 | El-Maleh, A.H. unknown |
| author2_role | author author |
| author_facet | Osais, Y.E. El-Maleh, A.H. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | Osais, Y.E. El-Maleh, A.H. unknown |
| dc.date.none.fl_str_mv | 2003-12 2020 |
| dc.format.none.fl_str_mv | application/pdf application/msword |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14098/1/14098_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14098/2/14098_2.doc (2003) A static test compaction technique for combinational circuits based on independent fault clustering. Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International conference, 3. |
| dc.language.none.fl_str_mv | en en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14098/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | A static test compaction technique for combinational circuits based on independent fault clustering |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | Testing system-on-chip involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. In this paper, a new static compaction algorithm for combinational circuits is presented. The algorithm is referred to as independent fault clustering. It is based on a new concept called test vector decomposition. Experimental results for benchmark circuits demonstrate the effectiveness of the new static compaction algorithm. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_1f1b199c1e080a98916b5678562931f3 |
| identifier_str_mv | (2003) A static test compaction technique for combinational circuits based on independent fault clustering. Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International conference, 3. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::14098 |
| publishDate | 2003 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | A static test compaction technique for combinational circuits based on independent fault clusteringOsais, Y.E.El-Maleh, A.H.unknownComputerTesting system-on-chip involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. In this paper, a new static compaction algorithm for combinational circuits is presented. The algorithm is referred to as independent fault clustering. It is based on a new concept called test vector decomposition. Experimental results for benchmark circuits demonstrate the effectiveness of the new static compaction algorithm.IEEE2003-122020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfapplication/mswordhttps://eprints.kfupm.edu.sa/id/eprint/14098/1/14098_1.pdfhttps://eprints.kfupm.edu.sa/id/eprint/14098/2/14098_2.doc (2003) A static test compaction technique for combinational circuits based on independent fault clustering. Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International conference, 3. enenhttps://eprints.kfupm.edu.sa/id/eprint/14098/info:eu-repo/semantics/openAccessoai::140982019-11-01T14:04:09Z |
| spellingShingle | A static test compaction technique for combinational circuits based on independent fault clustering Osais, Y.E. Computer |
| status_str | publishedVersion |
| title | A static test compaction technique for combinational circuits based on independent fault clustering |
| title_full | A static test compaction technique for combinational circuits based on independent fault clustering |
| title_fullStr | A static test compaction technique for combinational circuits based on independent fault clustering |
| title_full_unstemmed | A static test compaction technique for combinational circuits based on independent fault clustering |
| title_short | A static test compaction technique for combinational circuits based on independent fault clustering |
| title_sort | A static test compaction technique for combinational circuits based on independent fault clustering |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/14098/1/14098_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14098/2/14098_2.doc |