New fault models and efficient BIST algorithms for dual-portmemories
The testability problem of dual-port memories is investigated. A functional model is defined, and architectural modifications to enhance the testability of such chips are described. These modifications allow multiple access of memory cells for increased test speed with minimal overhead on both silic...
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| Format: | article |
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1997
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14841/1/14841_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14841/2/14841_2.doc |
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| _version_ | 1864513394316410880 |
|---|---|
| author | Amin, A.A. |
| author2 | Osman, M.Y. Abdel-Aal, R.E. Al-Muhtaseb, Husni unknown |
| author2_role | author author author author |
| author_facet | Amin, A.A. Osman, M.Y. Abdel-Aal, R.E. Al-Muhtaseb, Husni unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | Amin, A.A. Osman, M.Y. Abdel-Aal, R.E. Al-Muhtaseb, Husni unknown |
| dc.date.none.fl_str_mv | 1997-09 2020 |
| dc.format.none.fl_str_mv | application/pdf application/msword |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14841/1/14841_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14841/2/14841_2.doc (1997) New fault models and efficient BIST algorithms for dual-portmemories. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 16. |
| dc.language.none.fl_str_mv | en en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14841/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | New fault models and efficient BIST algorithms for dual-portmemories |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | The testability problem of dual-port memories is investigated. A functional model is defined, and architectural modifications to enhance the testability of such chips are described. These modifications allow multiple access of memory cells for increased test speed with minimal overhead on both silicon area and device performance. New fault models are proposed, and efficient O(n) test algorithms are described for both the memory array and the address decoders. The new fault models account for the simultaneous dual-access property of the device. In addition to the classical static neighborhood pattern-sensitive faults, the array test algorithm covers a new class of pattern sensitive faults, duplex dynamic neighborhood pattern-sensitive faults (DDNPSF) |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_2040b6656727f8e692308f99d948dffb |
| identifier_str_mv | (1997) New fault models and efficient BIST algorithms for dual-portmemories. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 16. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::14841 |
| publishDate | 1997 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | New fault models and efficient BIST algorithms for dual-portmemoriesAmin, A.A.Osman, M.Y.Abdel-Aal, R.E.Al-Muhtaseb, HusniunknownComputerThe testability problem of dual-port memories is investigated. A functional model is defined, and architectural modifications to enhance the testability of such chips are described. These modifications allow multiple access of memory cells for increased test speed with minimal overhead on both silicon area and device performance. New fault models are proposed, and efficient O(n) test algorithms are described for both the memory array and the address decoders. The new fault models account for the simultaneous dual-access property of the device. In addition to the classical static neighborhood pattern-sensitive faults, the array test algorithm covers a new class of pattern sensitive faults, duplex dynamic neighborhood pattern-sensitive faults (DDNPSF)IEEE1997-092020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfapplication/mswordhttps://eprints.kfupm.edu.sa/id/eprint/14841/1/14841_1.pdfhttps://eprints.kfupm.edu.sa/id/eprint/14841/2/14841_2.doc (1997) New fault models and efficient BIST algorithms for dual-portmemories. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 16. enenhttps://eprints.kfupm.edu.sa/id/eprint/14841/info:eu-repo/semantics/openAccessoai::148412019-11-01T14:07:42Z |
| spellingShingle | New fault models and efficient BIST algorithms for dual-portmemories Amin, A.A. Computer |
| status_str | publishedVersion |
| title | New fault models and efficient BIST algorithms for dual-portmemories |
| title_full | New fault models and efficient BIST algorithms for dual-portmemories |
| title_fullStr | New fault models and efficient BIST algorithms for dual-portmemories |
| title_full_unstemmed | New fault models and efficient BIST algorithms for dual-portmemories |
| title_short | New fault models and efficient BIST algorithms for dual-portmemories |
| title_sort | New fault models and efficient BIST algorithms for dual-portmemories |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/14841/1/14841_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14841/2/14841_2.doc |