Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration
This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan recon...
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| _version_ | 1864513402795196416 |
|---|---|
| author | Al-Yamani, A. |
| author2 | Devta-Prasanna, N. Chmelar, E. Grinchuk, M. Gunda, A. unknown |
| author2_role | author author author author author |
| author_facet | Al-Yamani, A. Devta-Prasanna, N. Chmelar, E. Grinchuk, M. Gunda, A. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | Al-Yamani, A. Devta-Prasanna, N. Chmelar, E. Grinchuk, M. Gunda, A. unknown |
| dc.date.none.fl_str_mv | 0000-05 2020 |
| dc.format.none.fl_str_mv | application/pdf application/msword |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14310/1/14310_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14310/2/14310_2.doc (0000) Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 26. |
| dc.language.none.fl_str_mv | en en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14310/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10times to 40 times compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test sets |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_24511fc4136798122e10d84032c81c09 |
| identifier_str_mv | (0000) Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 26. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::14310 |
| publishDate | 0000 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | Scan Test Cost and Power Reduction Through Systematic Scan ReconfigurationAl-Yamani, A.Devta-Prasanna, N.Chmelar, E.Grinchuk, M.Gunda, A.unknownComputerThis paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10times to 40 times compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test setsIEEE0000-052020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfapplication/mswordhttps://eprints.kfupm.edu.sa/id/eprint/14310/1/14310_1.pdfhttps://eprints.kfupm.edu.sa/id/eprint/14310/2/14310_2.doc (0000) Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 26. enenhttps://eprints.kfupm.edu.sa/id/eprint/14310/info:eu-repo/semantics/openAccessoai::143102019-11-01T14:05:16Z |
| spellingShingle | Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration Al-Yamani, A. Computer |
| status_str | publishedVersion |
| title | Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration |
| title_full | Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration |
| title_fullStr | Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration |
| title_full_unstemmed | Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration |
| title_short | Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration |
| title_sort | Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/14310/1/14310_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14310/2/14310_2.doc |