BIT-SLICE MICROPROCESSOR-BASED COMMUNICATIONS DECODER
Abstract The hardware design of a bit-slice microprocessor-based realtime cyclic error-correcting communications decoder is presented. A microprocessor-based architecture is preferred because of its programmability, low cost and simplicity of design. To augment the throughput of the decoder for real...
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| Other Authors: | , , |
| Format: | article |
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2020
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/303/1/bit_slice.pdf |
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| Summary: | Abstract The hardware design of a bit-slice microprocessor-based realtime cyclic error-correcting communications decoder is presented. A microprocessor-based architecture is preferred because of its programmability, low cost and simplicity of design. To augment the throughput of the decoder for realtime decoding, the ALU word length is chosen to be equal to that of a code word and the decoding operation is accomplished in two steps, i.e. error detection and error correction. A buffer memory stores incoming blocks as more than one block may be received during a decoding cycle. The design is versatile: different decoding algorithms can be executed by changing the microprogram. Only simple changes in the design are necessary to decode words of longer block length. Keywords: microprocessors; digital communications; decoding |
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