A Parallel Algorithm for Inverse Halftoning and its Hardware Implementation

Abstract Lookup Table (LUT) method for inverse halftoning is computation less, fast and also yields goods results. This paper proposes a parallel algorithm for inverse halftoning by parallelizing the LUT method of inverse halftoning. The LUT method for inverse halftoning is parallelized by dividing...

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محفوظ في:
التفاصيل البيبلوغرافية
المؤلف الرئيسي: Siddiqi, Umair F. (author)
مؤلفون آخرون: Sait, Sadiq M. (author), unknown (author)
التنسيق: article
منشور في: 2020
الموضوعات:
الوصول للمادة أونلاين:https://eprints.kfupm.edu.sa/id/eprint/254/1/J_Siddiqui_AJSE_December2006.pdf
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author Siddiqi, Umair F.
author2 Sait, Sadiq M.
unknown
author2_role author
author
author_facet Siddiqi, Umair F.
Sait, Sadiq M.
unknown
author_role author
dc.creator.none.fl_str_mv Siddiqi, Umair F.
Sait, Sadiq M.
unknown
dc.date.*.fl_str_mv 2020
dc.format.none.fl_str_mv application/pdf
dc.identifier.none.fl_str_mv https://eprints.kfupm.edu.sa/id/eprint/254/1/J_Siddiqui_AJSE_December2006.pdf
A Parallel Algorithm for Inverse Halftoning and its Hardware Implementation. Arabian Journal of Science and Engineering (AJSE) Submitted Dec 2006.
dc.language.none.fl_str_mv en
dc.relation.none.fl_str_mv https://eprints.kfupm.edu.sa/id/eprint/254/
dc.rights.*.fl_str_mv info:eu-repo/semantics/openAccess
dc.subject.none.fl_str_mv Computer
dc.title.none.fl_str_mv A Parallel Algorithm for Inverse Halftoning and its Hardware Implementation
dc.type.none.fl_str_mv Article
PeerReviewed
info:eu-repo/semantics/publishedVersion
info:eu-repo/semantics/article
description Abstract Lookup Table (LUT) method for inverse halftoning is computation less, fast and also yields goods results. This paper proposes a parallel algorithm for inverse halftoning by parallelizing the LUT method of inverse halftoning. The LUT method for inverse halftoning is parallelized by dividing the single Look-Up Table of LUT method for inverse halftoning into many smaller Look-up Tables (sLUTs). In the parallel algorithm up-to four pixels can be fetched from the halftone image concurrently and go to their separate smaller Look-Up Tables (sLUT) from where each template fetches its inverse halftone value independent to other pixels. The parallelization can increase the speed of inverse halftoning by up-to 4 times while the total entries in all smaller Look-Up Tables (sLUTs) remains equal to the entries in the single LUT of LUT method for inverse halftoning. Some degradation in image quality is noticed due to parallelization. The complete implementation of the method takes two CPLD devices with external content addressable memories (CAM) and static RAMs to store sLUTs. Keywords: (1) Inverse Halftoning (2) Hardware Implementation (3) Look-Up Table Inverse Halftoning (4) Complex Programmable Logic Devices (CPLD) (5) Image Processing
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identifier_str_mv A Parallel Algorithm for Inverse Halftoning and its Hardware Implementation. Arabian Journal of Science and Engineering (AJSE) Submitted Dec 2006.
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network_acronym_str KFUPM
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spelling A Parallel Algorithm for Inverse Halftoning and its Hardware ImplementationSiddiqi, Umair F.Sait, Sadiq M.unknownComputerAbstract Lookup Table (LUT) method for inverse halftoning is computation less, fast and also yields goods results. This paper proposes a parallel algorithm for inverse halftoning by parallelizing the LUT method of inverse halftoning. The LUT method for inverse halftoning is parallelized by dividing the single Look-Up Table of LUT method for inverse halftoning into many smaller Look-up Tables (sLUTs). In the parallel algorithm up-to four pixels can be fetched from the halftone image concurrently and go to their separate smaller Look-Up Tables (sLUT) from where each template fetches its inverse halftone value independent to other pixels. The parallelization can increase the speed of inverse halftoning by up-to 4 times while the total entries in all smaller Look-Up Tables (sLUTs) remains equal to the entries in the single LUT of LUT method for inverse halftoning. Some degradation in image quality is noticed due to parallelization. The complete implementation of the method takes two CPLD devices with external content addressable memories (CAM) and static RAMs to store sLUTs. Keywords: (1) Inverse Halftoning (2) Hardware Implementation (3) Look-Up Table Inverse Halftoning (4) Complex Programmable Logic Devices (CPLD) (5) Image ProcessingArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttps://eprints.kfupm.edu.sa/id/eprint/254/1/J_Siddiqui_AJSE_December2006.pdf A Parallel Algorithm for Inverse Halftoning and its Hardware Implementation. Arabian Journal of Science and Engineering (AJSE) Submitted Dec 2006. enhttps://eprints.kfupm.edu.sa/id/eprint/254/2020info:eu-repo/semantics/openAccessoai::2542019-11-01T13:23:14Z
spellingShingle A Parallel Algorithm for Inverse Halftoning and its Hardware Implementation
Siddiqi, Umair F.
Computer
status_str publishedVersion
title A Parallel Algorithm for Inverse Halftoning and its Hardware Implementation
title_full A Parallel Algorithm for Inverse Halftoning and its Hardware Implementation
title_fullStr A Parallel Algorithm for Inverse Halftoning and its Hardware Implementation
title_full_unstemmed A Parallel Algorithm for Inverse Halftoning and its Hardware Implementation
title_short A Parallel Algorithm for Inverse Halftoning and its Hardware Implementation
title_sort A Parallel Algorithm for Inverse Halftoning and its Hardware Implementation
topic Computer
url https://eprints.kfupm.edu.sa/id/eprint/254/1/J_Siddiqui_AJSE_December2006.pdf