On Test Vector Reordering for Combinational Circuits
The cost of testing is a major factor in the cost of digital system design. In order to reduce the test application time, it is required to order the test vectors in such away that reduces the time a defective chip spends on a tester until the defect is detected. In this paper, we propose an efficie...
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2004
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/164/1/On_Test_Vector_Reordering_for_Combinational_Circuits_ICM2004.pdf |
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| _version_ | 1864513379788390400 |
|---|---|
| author | El-Maleh, Aiman H. |
| author2 | Osais, Yahya E. unknown |
| author2_role | author author |
| author_facet | El-Maleh, Aiman H. Osais, Yahya E. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | El-Maleh, Aiman H. Osais, Yahya E. unknown |
| dc.date.none.fl_str_mv | 2004-12 2020 |
| dc.format.none.fl_str_mv | application/pdf |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/164/1/On_Test_Vector_Reordering_for_Combinational_Circuits_ICM2004.pdf (2004) On Test Vector Reordering for Combinational Circuits. 16th International Conference on Microelectronics. 772 -775. |
| dc.language.none.fl_str_mv | en |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/164/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | On Test Vector Reordering for Combinational Circuits |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | The cost of testing is a major factor in the cost of digital system design. In order to reduce the test application time, it is required to order the test vectors in such away that reduces the time a defective chip spends on a tester until the defect is detected. In this paper, we propose an efficient test vector reordering technique that significantly reduces both the time and memory complexities of reordering procedures based on fault simulation without dropping. Experimental results demonstrate both the efficiency and effectiveness of our proposed technique. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_4ba55b763e6adebfd290a67d07dd6460 |
| identifier_str_mv | (2004) On Test Vector Reordering for Combinational Circuits. 16th International Conference on Microelectronics. 772 -775. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::164 |
| publishDate | 2004 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | On Test Vector Reordering for Combinational CircuitsEl-Maleh, Aiman H.Osais, Yahya E.unknownComputerThe cost of testing is a major factor in the cost of digital system design. In order to reduce the test application time, it is required to order the test vectors in such away that reduces the time a defective chip spends on a tester until the defect is detected. In this paper, we propose an efficient test vector reordering technique that significantly reduces both the time and memory complexities of reordering procedures based on fault simulation without dropping. Experimental results demonstrate both the efficiency and effectiveness of our proposed technique.2004-122020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttps://eprints.kfupm.edu.sa/id/eprint/164/1/On_Test_Vector_Reordering_for_Combinational_Circuits_ICM2004.pdf (2004) On Test Vector Reordering for Combinational Circuits. 16th International Conference on Microelectronics. 772 -775. enhttps://eprints.kfupm.edu.sa/id/eprint/164/info:eu-repo/semantics/openAccessoai::1642019-11-01T13:22:42Z |
| spellingShingle | On Test Vector Reordering for Combinational Circuits El-Maleh, Aiman H. Computer |
| status_str | publishedVersion |
| title | On Test Vector Reordering for Combinational Circuits |
| title_full | On Test Vector Reordering for Combinational Circuits |
| title_fullStr | On Test Vector Reordering for Combinational Circuits |
| title_full_unstemmed | On Test Vector Reordering for Combinational Circuits |
| title_short | On Test Vector Reordering for Combinational Circuits |
| title_sort | On Test Vector Reordering for Combinational Circuits |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/164/1/On_Test_Vector_Reordering_for_Combinational_Circuits_ICM2004.pdf |