Iterative heuristics for multiobjective VLSI standard cellplacement
We employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuristics are based on genetic algorithms (GA) and tabu search (TS) respectively. We address a multiobjective version of the problem, in which power dissipation, timing performance, and interconnect wire...
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2001
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14554/1/14554_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14554/2/14554_2.doc |
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| _version_ | 1864513402867548160 |
|---|---|
| author | Sait, Sadiq M. |
| author2 | Youssef, H. El-Maleh, A.H. Minhas, M.R. unknown |
| author2_role | author author author author |
| author_facet | Sait, Sadiq M. Youssef, H. El-Maleh, A.H. Minhas, M.R. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | Sait, Sadiq M. Youssef, H. El-Maleh, A.H. Minhas, M.R. unknown |
| dc.date.none.fl_str_mv | 2001 2020 |
| dc.format.none.fl_str_mv | application/pdf application/msword |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14554/1/14554_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14554/2/14554_2.doc (2001) Iterative heuristics for multiobjective VLSI standard cellplacement. Neural Networks, 2001. Proceedings. IJCNN '01. International Joint conference, 3. |
| dc.language.none.fl_str_mv | en en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14554/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | Iterative heuristics for multiobjective VLSI standard cellplacement |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | We employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuristics are based on genetic algorithms (GA) and tabu search (TS) respectively. We address a multiobjective version of the problem, in which power dissipation, timing performance, and interconnect wire length are optimized while layout width is taken as a constraint. Fuzzy rules are incorporated in order to design a multiobjective cost function that integrates the costs of three objectives in a single overall cost value. A series of experiments is performed to study the effect of important algorithmic parameters of GA and TS. Both the techniques are applied to ISCAS-85/89 benchmark circuits and experimental results are reported and compared |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_4ce2131614f0c0084d35f3e7e951c93a |
| identifier_str_mv | (2001) Iterative heuristics for multiobjective VLSI standard cellplacement. Neural Networks, 2001. Proceedings. IJCNN '01. International Joint conference, 3. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::14554 |
| publishDate | 2001 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | Iterative heuristics for multiobjective VLSI standard cellplacementSait, Sadiq M.Youssef, H.El-Maleh, A.H.Minhas, M.R.unknownComputerWe employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuristics are based on genetic algorithms (GA) and tabu search (TS) respectively. We address a multiobjective version of the problem, in which power dissipation, timing performance, and interconnect wire length are optimized while layout width is taken as a constraint. Fuzzy rules are incorporated in order to design a multiobjective cost function that integrates the costs of three objectives in a single overall cost value. A series of experiments is performed to study the effect of important algorithmic parameters of GA and TS. Both the techniques are applied to ISCAS-85/89 benchmark circuits and experimental results are reported and comparedIEEE20012020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfapplication/mswordhttps://eprints.kfupm.edu.sa/id/eprint/14554/1/14554_1.pdfhttps://eprints.kfupm.edu.sa/id/eprint/14554/2/14554_2.doc (2001) Iterative heuristics for multiobjective VLSI standard cellplacement. Neural Networks, 2001. Proceedings. IJCNN '01. International Joint conference, 3. enenhttps://eprints.kfupm.edu.sa/id/eprint/14554/info:eu-repo/semantics/openAccessoai::145542019-11-01T14:06:22Z |
| spellingShingle | Iterative heuristics for multiobjective VLSI standard cellplacement Sait, Sadiq M. Computer |
| status_str | publishedVersion |
| title | Iterative heuristics for multiobjective VLSI standard cellplacement |
| title_full | Iterative heuristics for multiobjective VLSI standard cellplacement |
| title_fullStr | Iterative heuristics for multiobjective VLSI standard cellplacement |
| title_full_unstemmed | Iterative heuristics for multiobjective VLSI standard cellplacement |
| title_short | Iterative heuristics for multiobjective VLSI standard cellplacement |
| title_sort | Iterative heuristics for multiobjective VLSI standard cellplacement |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/14554/1/14554_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14554/2/14554_2.doc |