APA (7th ed.) Citation

Sait, S. M., Khan, J. A., & unknown. (2020). Simulated evolution for timing and low power VLSI standard cell placement.

Chicago Style (17th ed.) Citation

Sait, Sadiq M., Junaid A. Khan, and unknown. Simulated Evolution for Timing and Low Power VLSI Standard Cell Placement. 2020.

MLA (9th ed.) Citation

Sait, Sadiq M., et al. Simulated Evolution for Timing and Low Power VLSI Standard Cell Placement. 2020.