Simulated evolution for timing and low power VLSI standard cell placement
Abstract This paper presents a Fuzzy Simulated Evolution algorithm for VLSI standard cell placement with the objective of minimizing power, delay and area. For this hard multiobjective combinatorial optimization problem, no known exact and efficient algorithms exist that guarantee finding a solution...
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| Other Authors: | , |
| Format: | article |
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2020
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/267/1/J_Sait_EAAI_August2003.pdf |
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| _version_ | 1864513379814604800 |
|---|---|
| author | Sait, Sadiq M. |
| author2 | Khan, Junaid A. unknown |
| author2_role | author author |
| author_facet | Sait, Sadiq M. Khan, Junaid A. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | Sait, Sadiq M. Khan, Junaid A. unknown |
| dc.date.*.fl_str_mv | 2020 |
| dc.format.none.fl_str_mv | application/pdf |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/267/1/J_Sait_EAAI_August2003.pdf Simulated evolution for timing and low power VLSI standard cell placement. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 16 (5-6): 407-423 AUG-SEP 2003. |
| dc.language.none.fl_str_mv | en |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/267/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | Simulated evolution for timing and low power VLSI standard cell placement |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | Abstract This paper presents a Fuzzy Simulated Evolution algorithm for VLSI standard cell placement with the objective of minimizing power, delay and area. For this hard multiobjective combinatorial optimization problem, no known exact and efficient algorithms exist that guarantee finding a solution of specific or desirable quality. Approximation iterative heuristics such as Simulated Evolution are best suited to perform an intelligent search of the solution space. Due to the imprecise nature of design information at the placement stage the various objectives and constraints are expressed in the fuzzy domain. The search is made to evolve toward a vector of fuzzy goals. Variants of the algorithm which include adaptive bias and biasless simulated evolution are proposed and experimental results are presented. Comparison with genetic algorithm is discussed. r 2003 Elsevier Ltd. All rights reserved. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_5697fb4a6f269b45c42ca450a9cd9725 |
| identifier_str_mv | Simulated evolution for timing and low power VLSI standard cell placement. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 16 (5-6): 407-423 AUG-SEP 2003. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::267 |
| publishDate | 2020 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | Simulated evolution for timing and low power VLSI standard cell placementSait, Sadiq M.Khan, Junaid A.unknownComputerAbstract This paper presents a Fuzzy Simulated Evolution algorithm for VLSI standard cell placement with the objective of minimizing power, delay and area. For this hard multiobjective combinatorial optimization problem, no known exact and efficient algorithms exist that guarantee finding a solution of specific or desirable quality. Approximation iterative heuristics such as Simulated Evolution are best suited to perform an intelligent search of the solution space. Due to the imprecise nature of design information at the placement stage the various objectives and constraints are expressed in the fuzzy domain. The search is made to evolve toward a vector of fuzzy goals. Variants of the algorithm which include adaptive bias and biasless simulated evolution are proposed and experimental results are presented. Comparison with genetic algorithm is discussed. r 2003 Elsevier Ltd. All rights reserved.ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttps://eprints.kfupm.edu.sa/id/eprint/267/1/J_Sait_EAAI_August2003.pdf Simulated evolution for timing and low power VLSI standard cell placement. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 16 (5-6): 407-423 AUG-SEP 2003. enhttps://eprints.kfupm.edu.sa/id/eprint/267/2020info:eu-repo/semantics/openAccessoai::2672019-11-01T13:23:20Z |
| spellingShingle | Simulated evolution for timing and low power VLSI standard cell placement Sait, Sadiq M. Computer |
| status_str | publishedVersion |
| title | Simulated evolution for timing and low power VLSI standard cell placement |
| title_full | Simulated evolution for timing and low power VLSI standard cell placement |
| title_fullStr | Simulated evolution for timing and low power VLSI standard cell placement |
| title_full_unstemmed | Simulated evolution for timing and low power VLSI standard cell placement |
| title_short | Simulated evolution for timing and low power VLSI standard cell placement |
| title_sort | Simulated evolution for timing and low power VLSI standard cell placement |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/267/1/J_Sait_EAAI_August2003.pdf |