An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose...
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| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | , |
| التنسيق: | article |
| منشور في: |
2002
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| الموضوعات: | |
| الوصول للمادة أونلاين: | https://eprints.kfupm.edu.sa/id/eprint/142/1/An_Efficient_Test_Relaxation_Technique_for_Combinational_Circuits_Based_on_Critical_Path_Tracing_icecs2002.pdf |
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| _version_ | 1864513399773200384 |
|---|---|
| author | El-Maleh, Aiman H. |
| author2 | Al-Suwaiyan, Ali unknown |
| author2_role | author author |
| author_facet | El-Maleh, Aiman H. Al-Suwaiyan, Ali unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | El-Maleh, Aiman H. Al-Suwaiyan, Ali unknown |
| dc.date.none.fl_str_mv | 2002-09 2020 |
| dc.format.none.fl_str_mv | application/pdf |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/142/1/An_Efficient_Test_Relaxation_Technique_for_Combinational_Circuits_Based_on_Critical_Path_Tracing_icecs2002.pdf (2002) An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing. 9th IEEE International Conference on Electronics, Circuits and Systems. pp. 461-465. |
| dc.language.none.fl_str_mv | en |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/142/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | Reducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational circuits. It is based on critical path tracing and hence it may result in a reduction in the fault coverage. However, based on experimental results on ISCAS benchmark circuits, the drop in the fault coverage (if any) after relaxation is small for most of the circuits. The technique is faster than the brute-force test relaxation method by several orders of magnitude. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_5817fb40800210b94f3292b24abacc7a |
| identifier_str_mv | (2002) An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing. 9th IEEE International Conference on Electronics, Circuits and Systems. pp. 461-465. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::142 |
| publishDate | 2002 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path TracingEl-Maleh, Aiman H.Al-Suwaiyan, AliunknownComputerReducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational circuits. It is based on critical path tracing and hence it may result in a reduction in the fault coverage. However, based on experimental results on ISCAS benchmark circuits, the drop in the fault coverage (if any) after relaxation is small for most of the circuits. The technique is faster than the brute-force test relaxation method by several orders of magnitude.2002-092020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttps://eprints.kfupm.edu.sa/id/eprint/142/1/An_Efficient_Test_Relaxation_Technique_for_Combinational_Circuits_Based_on_Critical_Path_Tracing_icecs2002.pdf (2002) An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing. 9th IEEE International Conference on Electronics, Circuits and Systems. pp. 461-465. enhttps://eprints.kfupm.edu.sa/id/eprint/142/info:eu-repo/semantics/openAccessoai::1422019-11-01T13:22:33Z |
| spellingShingle | An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing El-Maleh, Aiman H. Computer |
| status_str | publishedVersion |
| title | An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing |
| title_full | An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing |
| title_fullStr | An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing |
| title_full_unstemmed | An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing |
| title_short | An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing |
| title_sort | An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/142/1/An_Efficient_Test_Relaxation_Technique_for_Combinational_Circuits_Based_on_Critical_Path_Tracing_icecs2002.pdf |