An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing

An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing

Reducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose...

وصف كامل

محفوظ في:

التفاصيل البيبلوغرافية
المؤلف الرئيسي:	El-Maleh, Aiman H. (author)
مؤلفون آخرون:	Al-Suwaiyan, Ali (author), unknown (author)
التنسيق:	article
منشور في:	2002
الموضوعات:	Computer
الوصول للمادة أونلاين:	https://eprints.kfupm.edu.sa/id/eprint/142/1/An_Efficient_Test_Relaxation_Technique_for_Combinational_Circuits_Based_on_Critical_Path_Tracing_icecs2002.pdf
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