Interconnect-Efficient LDPC Code Design
In this paper, we present a new, hardware-oriented technique for designing Low Density Parity Check (LDPC) codes. The technique targets to achieve an interconnect-efficient architecture that reduces the area and delay of the decoder implementation while maintaining good error correction performance....
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | , , |
| Format: | article |
| Published: |
2006
|
| Subjects: | |
| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14136/1/14136_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14136/2/14136_2.doc |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|