Fault characterization and testability considerations inmulti-valued logic circuits
With the growing interest and the emergence of various implementations of Multiple-Valued logic (MVL) circuits, testability issues of these circuits are becoming crucial. Fault characterization is an early step in the test generation process. It is aimed at finding fault models that best describe th...
محفوظ في:
| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | , , |
| التنسيق: | article |
| منشور في: |
1999
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| الموضوعات: | |
| الوصول للمادة أونلاين: | https://eprints.kfupm.edu.sa/id/eprint/14028/1/14028_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14028/2/14028_2.doc |
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| _version_ | 1864513383776124928 |
|---|---|
| author | Abd-El-Barr, Mostafa |
| author2 | Al-Sherif, M. Osman, M. unknown |
| author2_role | author author author |
| author_facet | Abd-El-Barr, Mostafa Al-Sherif, M. Osman, M. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | Abd-El-Barr, Mostafa Al-Sherif, M. Osman, M. unknown |
| dc.date.none.fl_str_mv | 1999 2020 |
| dc.format.none.fl_str_mv | application/pdf application/msword |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14028/1/14028_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14028/2/14028_2.doc (1999) Fault characterization and testability considerations inmulti-valued logic circuits. Multiple-Valued Logic, 1999. Proceedings. 1999 29th IEEE International Symposium on, 1. |
| dc.language.none.fl_str_mv | en en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14028/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | Fault characterization and testability considerations inmulti-valued logic circuits |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | With the growing interest and the emergence of various implementations of Multiple-Valued logic (MVL) circuits, testability issues of these circuits are becoming crucial. Fault characterization is an early step in the test generation process. It is aimed at finding fault models that best describe the possible faults expected to occur in a given class of circuits or technology. Layout and device level studies on CMOS and BiCMOS circuits revealed that the stuck-at model is not adequate to represent the actual physical defects. In this paper our aim is to characterize faults in a CMOS functionally complete set of MVL operators. The set has been implemented using existing standard binary CMOS technology. This enables us to characterize faults in these operators using the same techniques used for standard binary CMOS. Fault categories in MVL circuits and recommendations for testability will be given |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_62047b762ab883af1dfce21af8dde72d |
| identifier_str_mv | (1999) Fault characterization and testability considerations inmulti-valued logic circuits. Multiple-Valued Logic, 1999. Proceedings. 1999 29th IEEE International Symposium on, 1. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::14028 |
| publishDate | 1999 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | Fault characterization and testability considerations inmulti-valued logic circuitsAbd-El-Barr, MostafaAl-Sherif, M.Osman, M.unknownComputerWith the growing interest and the emergence of various implementations of Multiple-Valued logic (MVL) circuits, testability issues of these circuits are becoming crucial. Fault characterization is an early step in the test generation process. It is aimed at finding fault models that best describe the possible faults expected to occur in a given class of circuits or technology. Layout and device level studies on CMOS and BiCMOS circuits revealed that the stuck-at model is not adequate to represent the actual physical defects. In this paper our aim is to characterize faults in a CMOS functionally complete set of MVL operators. The set has been implemented using existing standard binary CMOS technology. This enables us to characterize faults in these operators using the same techniques used for standard binary CMOS. Fault categories in MVL circuits and recommendations for testability will be givenIEEE19992020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfapplication/mswordhttps://eprints.kfupm.edu.sa/id/eprint/14028/1/14028_1.pdfhttps://eprints.kfupm.edu.sa/id/eprint/14028/2/14028_2.doc (1999) Fault characterization and testability considerations inmulti-valued logic circuits. Multiple-Valued Logic, 1999. Proceedings. 1999 29th IEEE International Symposium on, 1. enenhttps://eprints.kfupm.edu.sa/id/eprint/14028/info:eu-repo/semantics/openAccessoai::140282019-11-01T14:03:49Z |
| spellingShingle | Fault characterization and testability considerations inmulti-valued logic circuits Abd-El-Barr, Mostafa Computer |
| status_str | publishedVersion |
| title | Fault characterization and testability considerations inmulti-valued logic circuits |
| title_full | Fault characterization and testability considerations inmulti-valued logic circuits |
| title_fullStr | Fault characterization and testability considerations inmulti-valued logic circuits |
| title_full_unstemmed | Fault characterization and testability considerations inmulti-valued logic circuits |
| title_short | Fault characterization and testability considerations inmulti-valued logic circuits |
| title_sort | Fault characterization and testability considerations inmulti-valued logic circuits |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/14028/1/14028_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14028/2/14028_2.doc |