On efficient extraction of partially specified test sets for synchronous sequential circuits
Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount...
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| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | , |
| التنسيق: | article |
| منشور في: |
2003
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| الموضوعات: | |
| الوصول للمادة أونلاين: | https://eprints.kfupm.edu.sa/id/eprint/14799/1/14799_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14799/2/14799_2.doc |
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| _version_ | 1864513384505933824 |
|---|---|
| author | El-Maleh, A. |
| author2 | Al-Utaibi, K. unknown |
| author2_role | author author |
| author_facet | El-Maleh, A. Al-Utaibi, K. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | El-Maleh, A. Al-Utaibi, K. unknown |
| dc.date.none.fl_str_mv | 2003-05 2020 |
| dc.format.none.fl_str_mv | application/pdf application/msword |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14799/1/14799_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14799/2/14799_2.doc (2003) On efficient extraction of partially specified test sets for synchronous sequential circuits. Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 5. |
| dc.language.none.fl_str_mv | en en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14799/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | On efficient extraction of partially specified test sets for synchronous sequential circuits |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. Relaxing test sequences, i.e. extracting partially specified test sequences, can improve the efficiency of both test compression and test compaction. In this paper, we propose an efficient test relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_70b867dacee109b75194ca8bde225f48 |
| identifier_str_mv | (2003) On efficient extraction of partially specified test sets for synchronous sequential circuits. Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 5. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::14799 |
| publishDate | 2003 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | On efficient extraction of partially specified test sets for synchronous sequential circuitsEl-Maleh, A.Al-Utaibi, K.unknownComputerTesting systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. Relaxing test sequences, i.e. extracting partially specified test sequences, can improve the efficiency of both test compression and test compaction. In this paper, we propose an efficient test relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set.IEEE2003-052020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfapplication/mswordhttps://eprints.kfupm.edu.sa/id/eprint/14799/1/14799_1.pdfhttps://eprints.kfupm.edu.sa/id/eprint/14799/2/14799_2.doc (2003) On efficient extraction of partially specified test sets for synchronous sequential circuits. Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 5. enenhttps://eprints.kfupm.edu.sa/id/eprint/14799/info:eu-repo/semantics/openAccessoai::147992019-11-01T14:07:32Z |
| spellingShingle | On efficient extraction of partially specified test sets for synchronous sequential circuits El-Maleh, A. Computer |
| status_str | publishedVersion |
| title | On efficient extraction of partially specified test sets for synchronous sequential circuits |
| title_full | On efficient extraction of partially specified test sets for synchronous sequential circuits |
| title_fullStr | On efficient extraction of partially specified test sets for synchronous sequential circuits |
| title_full_unstemmed | On efficient extraction of partially specified test sets for synchronous sequential circuits |
| title_short | On efficient extraction of partially specified test sets for synchronous sequential circuits |
| title_sort | On efficient extraction of partially specified test sets for synchronous sequential circuits |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/14799/1/14799_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14799/2/14799_2.doc |