A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit Design
—Tabu Search based cell placement approaches for VLSI circuit design have shown excellent results when executed on a single processor. However, they require signicant computation time. Of the various acceleration strategies attempted, parallelization has always exhibited the most potential. The para...
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| مؤلفون آخرون: | , |
| التنسيق: | article |
| منشور في: |
2020
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| الوصول للمادة أونلاين: | https://eprints.kfupm.edu.sa/id/eprint/1455/1/d2_s7_p2_1569047619.pdf |
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| _version_ | 1864513400566972416 |
|---|---|
| author | Sait, Sadiq M. |
| author2 | Syed, Sanaullah unknown |
| author2_role | author author |
| author_facet | Sait, Sadiq M. Syed, Sanaullah unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | Sait, Sadiq M. Syed, Sanaullah unknown |
| dc.date.*.fl_str_mv | 2020 |
| dc.format.none.fl_str_mv | application/pdf |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/1455/1/d2_s7_p2_1569047619.pdf A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit Design. IEEEGCC 2007. |
| dc.language.none.fl_str_mv | en |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/1455/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.title.none.fl_str_mv | A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit Design |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | —Tabu Search based cell placement approaches for VLSI circuit design have shown excellent results when executed on a single processor. However, they require signicant computation time. Of the various acceleration strategies attempted, parallelization has always exhibited the most potential. The parallel Tabu Search approach presented in this work can be classied as a synchronous master-slave p-control, RS and MPSS strategy. The approach is implemented on a dedicated Linux-based cluster of workstations, using MPI libraries for communication. Experimental results for ISCAS'89 benchmark circuits show excellent performance in terms of scalability & speed-up. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_712d6a68034074e9ddd43dd761674210 |
| identifier_str_mv | A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit Design. IEEEGCC 2007. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::1455 |
| publishDate | 2020 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit DesignSait, Sadiq M.Syed, Sanaullahunknown—Tabu Search based cell placement approaches for VLSI circuit design have shown excellent results when executed on a single processor. However, they require signicant computation time. Of the various acceleration strategies attempted, parallelization has always exhibited the most potential. The parallel Tabu Search approach presented in this work can be classied as a synchronous master-slave p-control, RS and MPSS strategy. The approach is implemented on a dedicated Linux-based cluster of workstations, using MPI libraries for communication. Experimental results for ISCAS'89 benchmark circuits show excellent performance in terms of scalability & speed-up.ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttps://eprints.kfupm.edu.sa/id/eprint/1455/1/d2_s7_p2_1569047619.pdf A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit Design. IEEEGCC 2007. enhttps://eprints.kfupm.edu.sa/id/eprint/1455/2020info:eu-repo/semantics/openAccessoai::14552019-11-01T13:27:01Z |
| spellingShingle | A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit Design Sait, Sadiq M. |
| status_str | publishedVersion |
| title | A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit Design |
| title_full | A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit Design |
| title_fullStr | A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit Design |
| title_full_unstemmed | A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit Design |
| title_short | A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit Design |
| title_sort | A Parallel Tabu Search Strategy for Cell Placement in VLSI Circuit Design |
| url | https://eprints.kfupm.edu.sa/id/eprint/1455/1/d2_s7_p2_1569047619.pdf |