ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS
Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount...
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | , |
| Format: | article |
| Published: |
2003
|
| Subjects: | |
| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/163/1/ON_EFFICIENT_EXTRACTION_OF_PARTIALLY_SPECIFIED_TEST_SETS_FOR_SYNCHRONOUS_SEQUENTIAL_CIRCUITS_ISCAS2003.pdf |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1864513379786293248 |
|---|---|
| author | El-Maleh, Aiman H. |
| author2 | Al-Utaibi, Khaled unknown |
| author2_role | author author |
| author_facet | El-Maleh, Aiman H. Al-Utaibi, Khaled unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | El-Maleh, Aiman H. Al-Utaibi, Khaled unknown |
| dc.date.none.fl_str_mv | 2003 2020 |
| dc.format.none.fl_str_mv | application/pdf |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/163/1/ON_EFFICIENT_EXTRACTION_OF_PARTIALLY_SPECIFIED_TEST_SETS_FOR_SYNCHRONOUS_SEQUENTIAL_CIRCUITS_ISCAS2003.pdf (2003) ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS. IEEE International Symposium on Circuits and Systems. V-545 -V-548. |
| dc.language.none.fl_str_mv | en |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/163/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. Relaxing test sequences, i.e. extracting partially specified test sequences, can improve the efficiency of both test compression and test compaction. In this paper, we propose an efficient test relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_7268cc5dec41dabc7f848942ba4342c9 |
| identifier_str_mv | (2003) ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS. IEEE International Symposium on Circuits and Systems. V-545 -V-548. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::163 |
| publishDate | 2003 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITSEl-Maleh, Aiman H.Al-Utaibi, KhaledunknownComputerTesting systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. Relaxing test sequences, i.e. extracting partially specified test sequences, can improve the efficiency of both test compression and test compaction. In this paper, we propose an efficient test relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set.20032020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttps://eprints.kfupm.edu.sa/id/eprint/163/1/ON_EFFICIENT_EXTRACTION_OF_PARTIALLY_SPECIFIED_TEST_SETS_FOR_SYNCHRONOUS_SEQUENTIAL_CIRCUITS_ISCAS2003.pdf (2003) ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS. IEEE International Symposium on Circuits and Systems. V-545 -V-548. enhttps://eprints.kfupm.edu.sa/id/eprint/163/info:eu-repo/semantics/openAccessoai::1632019-11-01T13:22:42Z |
| spellingShingle | ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS El-Maleh, Aiman H. Computer |
| status_str | publishedVersion |
| title | ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS |
| title_full | ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS |
| title_fullStr | ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS |
| title_full_unstemmed | ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS |
| title_short | ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS |
| title_sort | ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/163/1/ON_EFFICIENT_EXTRACTION_OF_PARTIALLY_SPECIFIED_TEST_SETS_FOR_SYNCHRONOUS_SEQUENTIAL_CIRCUITS_ISCAS2003.pdf |