Design Feasibility Study For A 500 Gbits/s AES Cypher Decypher Engine
A feasibility study for implementing the AES encryption algorithm in hardware achieving 500 Gbits/s is presented. The methodology followed in the process of obtaining the solution allowed us to reach a highly regular solution that is scalable.
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| Format: | article |
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2006
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14483/1/14483_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14483/2/14483_2.doc |
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