VLSI layout generation of a programmable CRC chip
VLSI layout generation of a programmable CRC chip with a CRC of 16-bits is presented. The hardware of CRC generator is specified in a hardware description language (HDL). The hardware compiler and functional level simulator of HDL are used for logic synthesis. The second stage of the compilation pro...
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| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | , |
| التنسيق: | article |
| منشور في: |
1993
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| الموضوعات: | |
| الوصول للمادة أونلاين: | https://eprints.kfupm.edu.sa/id/eprint/14242/1/14242_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14242/2/14242_2.doc |
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| _version_ | 1864513393649516544 |
|---|---|
| author | Sait, Sadiq M. |
| author2 | Tanvir, M.S.K. unknown |
| author2_role | author author |
| author_facet | Sait, Sadiq M. Tanvir, M.S.K. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | Sait, Sadiq M. Tanvir, M.S.K. unknown |
| dc.date.none.fl_str_mv | 1993-11 2020 |
| dc.format.none.fl_str_mv | application/pdf application/msword |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14242/1/14242_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14242/2/14242_2.doc (1993) VLSI layout generation of a programmable CRC chip. Consumer Electronics, IEEE Transactions on, 39. |
| dc.language.none.fl_str_mv | en en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14242/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | VLSI layout generation of a programmable CRC chip |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | VLSI layout generation of a programmable CRC chip with a CRC of 16-bits is presented. The hardware of CRC generator is specified in a hardware description language (HDL). The hardware compiler and functional level simulator of HDL are used for logic synthesis. The second stage of the compilation process generates a net list of logic gates. The net list so produced is translated to RNL compatible net list by a translator program. The layout subsystem of VPNR is used to generate the VLSI layout of the programmable CRC chip from RNL netlist. The design rules and technology files of MOSIS are used. The layout is viewed in the MAGIC layout editor and simulated by irsim at the transistor-level. The CRC chip can be used in a number of applications. These include areas such as data communications for error detection and correction, digital system testing for test pattern generation and signature analysis, and mass storage devices for parallel information transfers |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_7cd039094060f5c5d8c462a56ac84b6b |
| identifier_str_mv | (1993) VLSI layout generation of a programmable CRC chip. Consumer Electronics, IEEE Transactions on, 39. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::14242 |
| publishDate | 1993 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | VLSI layout generation of a programmable CRC chipSait, Sadiq M.Tanvir, M.S.K.unknownComputerVLSI layout generation of a programmable CRC chip with a CRC of 16-bits is presented. The hardware of CRC generator is specified in a hardware description language (HDL). The hardware compiler and functional level simulator of HDL are used for logic synthesis. The second stage of the compilation process generates a net list of logic gates. The net list so produced is translated to RNL compatible net list by a translator program. The layout subsystem of VPNR is used to generate the VLSI layout of the programmable CRC chip from RNL netlist. The design rules and technology files of MOSIS are used. The layout is viewed in the MAGIC layout editor and simulated by irsim at the transistor-level. The CRC chip can be used in a number of applications. These include areas such as data communications for error detection and correction, digital system testing for test pattern generation and signature analysis, and mass storage devices for parallel information transfersIEEE1993-112020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfapplication/mswordhttps://eprints.kfupm.edu.sa/id/eprint/14242/1/14242_1.pdfhttps://eprints.kfupm.edu.sa/id/eprint/14242/2/14242_2.doc (1993) VLSI layout generation of a programmable CRC chip. Consumer Electronics, IEEE Transactions on, 39. enenhttps://eprints.kfupm.edu.sa/id/eprint/14242/info:eu-repo/semantics/openAccessoai::142422019-11-01T14:04:53Z |
| spellingShingle | VLSI layout generation of a programmable CRC chip Sait, Sadiq M. Computer |
| status_str | publishedVersion |
| title | VLSI layout generation of a programmable CRC chip |
| title_full | VLSI layout generation of a programmable CRC chip |
| title_fullStr | VLSI layout generation of a programmable CRC chip |
| title_full_unstemmed | VLSI layout generation of a programmable CRC chip |
| title_short | VLSI layout generation of a programmable CRC chip |
| title_sort | VLSI layout generation of a programmable CRC chip |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/14242/1/14242_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14242/2/14242_2.doc |