VLSI layout generation of a programmable CRC chip
VLSI layout generation of a programmable CRC chip with a CRC of 16-bits is presented. The hardware of CRC generator is specified in a hardware description language (HDL). The hardware compiler and functional level simulator of HDL are used for logic synthesis. The second stage of the compilation pro...
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| Format: | article |
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1993
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14242/1/14242_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14242/2/14242_2.doc |
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