An Efficient test-pattern relaxation technique for synchronous sequential circuits

An Efficient test-pattern relaxation technique for synchronous sequential circuits

محفوظ في:

التفاصيل البيبلوغرافية
المؤلف الرئيسي:	Al-Utaibi, Khaled Abdul-Aziz (author)
مؤلفون آخرون:	unknown (author)
التنسيق:	masterThesis
منشور في:	2002
الموضوعات:	Computer
الوصول للمادة أونلاين:	https://eprints.kfupm.edu.sa/id/eprint/10432/1/10432.pdf
الوسوم:	إضافة وسم لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!

مواد مشابهة

An Efficient Test Relaxation Technique for Synchronous Sequential Circuits
حسب: El-Maleh, Aiman H.
منشور في: (2004)

An efficient test relaxation technique for synchronous sequential circuits
حسب: El-Maleh, A.
منشور في: (2003)

An Efficient Test Relaxation Technique for Synchronous Sequential Circuits
حسب: El-Maleh, Aiman H.
منشور في: (2003)

An efficient test relaxation technique for combinational & full-scan sequential circuits
حسب: El-Maleh, A.
منشور في: (2002)

An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits
حسب: El-Maleh, Aiman H.
منشور في: (2002)

Efficient static compaction techniques for sequential circuits based on reverse-order restoration and test relaxation
حسب: El-Maleh, Aiman H.
منشور في: (2006)

Test set compaction for sequential circuits based on test relaxation
حسب: Khursheed, Syed Saqib
منشور في: (2004)

ON EFFICIENT EXTRACTION OF PARTIALLY SPECIFIED TEST SETS FOR SYNCHRONOUS SEQUENTIAL CIRCUITS
حسب: El-Maleh, Aiman H.
منشور في: (2003)

On efficient extraction of partially specified test sets for synchronous sequential circuits
حسب: El-Maleh, A.
منشور في: (2003)

Efficient test relaxation techniques for combinational logic circuits
حسب: Al-Suwaiyan, Ali Saleh Mohammed
منشور في: (2002)

AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITS
حسب: El-Maleh, Aiman
منشور في: (2020)

An efficient test relaxation technique for combinational circuits based on critical path tracing
حسب: El-Maleh, A.
منشور في: (2002)

An Efficient Test Relaxation Technique for Combinational Circuits Based on Critical Path Tracing
حسب: El-Maleh, Aiman H.
منشور في: (2002)

Efficient static test compaction algorithms for combinational circuits based on test relaxation
حسب: Osais, Yahya Esmail
منشور في: (2003)

Fault Tolerance Techniques for Sequential Circuits: a Design Level Approach
حسب: Al-Qahtani, Ayed Saad
منشور في: (2010)

Evolutionary algorithms for state justification in sequential automatic test pattern generation
حسب: El-Maleh, Aiman H.
منشور في: (2005)

An Evolutionary Meta-Heuristic for State Justification in Sequential Automatic Test Pattern Generation
حسب: El-Maleh, Aiman H.
منشور في: (2001)

An Iterative Heuristic for State Justi�cation in Sequential Automatic Test Pattern Generation
حسب: El-Maleh, Aiman H.
منشور في: (2001)

A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance
حسب: El-Maleh, Aiman H.
منشور في: (1998)

A static test compaction technique for combinational circuits based on independent fault clustering
حسب: Osais, Y.E.
منشور في: (2003)

Efficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering
حسب: El-Maleh, Aiman H.
منشور في: (2006)

Efficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering
حسب: El-Maleh, Aiman H.
منشور في: (2007)

On Test Vector Reordering for Combinational Circuits
حسب: El-Maleh, Aiman H.
منشور في: (2004)

On test vector reordering for combinational circuits
حسب: El-Maleh, A.H.
منشور في: (2004)

A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decomposition
حسب: El-Maleh, Aiman H.
منشور في: (2007)

A hybrid test compression technique for efficient testing of systems-on-a-chip
حسب: El-Maleh, A.H.
منشور في: (2003)

A Hybrid Test Compression Technique for Efficient Testing of Systems-on-a-Chip
حسب: El-Maleh, Aiman H.
منشور في: (2003)

Efficient Test Compression Technique Based on Block Merging
حسب: El-Maleh, A. H.
منشور في: (2008)

An Efficient Test Vector Compression Technique Based on Geometric Shapes
حسب: Al Zahir, Saif
منشور في: (2001)

Circuit Techniques for Power Efficient Energy Harvesting Rectifiers
حسب: unknown
منشور في: (2020)

An Efficient Test Vector Compression Technique Based on Block Merging
حسب: El-Maleh, Aiman H.
منشور في: (2006)

A fault independent test generation method for combinational logic circuits
حسب: Al-Deeb, Mohamed Mahdy
منشور في: (1992)

A Fault Independent Test Generation Method For Combinational Logic Circuits
حسب: Al-Deeb, Mohamed Mahdy
منشور في: (1992)

A Digital Clock Re-Timing Circuit for On-Chip Source-Synchronous Serial Links
حسب: Elrabaa, Muhammad
منشور في: (2006)

The Successive Over-Relaxation Method in Reconfigurable Hardware
حسب: Haraty, Ramzi A.
منشور في: (2007)

Test Vector Decomposition Based Static Compaction Algorithms for Combinational Circuits
حسب: El-Maleh, Aiman H.
منشور في: (2003)

Sequential injection analysis technique for industrial water quality control
حسب: Legemah, Magnus U.
منشور في: (2006)

Efficient techniques for testing networks on chips. (c2010)
حسب: Abou Eid, Nancy
منشور في: (2010)

SOFTWARE REFACTORING USING PATTERN RECOGNITION TECHNIQUES
حسب: Alkhalid, Abdulaziz
منشور في: (2009)

A class-based clustering static compaction technique for combinational circuits
حسب: El-Maleh, A.H.
منشور في: (2004)