Design, selection and implementation of flash erase EEPROM memorycells
The author reports an investigation into the design and process constraints of flash EEPROM memory cells. He describes several possible structures which were developed by the MOS memory RD group of National Semiconductor Corporation at West Jordan, Utah. These structures were implemented and tested...
محفوظ في:
| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | |
| التنسيق: | article |
| منشور في: |
1992
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| الموضوعات: | |
| الوصول للمادة أونلاين: | https://eprints.kfupm.edu.sa/id/eprint/14481/1/14481_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14481/2/14481_2.doc |
| الوسوم: |
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| _version_ | 1864513393804705792 |
|---|---|
| author | Amin, A.A.M. |
| author2 | unknown |
| author2_role | author |
| author_facet | Amin, A.A.M. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | Amin, A.A.M. unknown |
| dc.date.none.fl_str_mv | 1992-06 2020 |
| dc.format.none.fl_str_mv | application/pdf application/msword |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14481/1/14481_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14481/2/14481_2.doc (1992) Design, selection and implementation of flash erase EEPROM memorycells. Circuits, Devices and Systems, IEE Proceedings G, 139. |
| dc.language.none.fl_str_mv | en en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14481/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | Design, selection and implementation of flash erase EEPROM memorycells |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | The author reports an investigation into the design and process constraints of flash EEPROM memory cells. He describes several possible structures which were developed by the MOS memory RD group of National Semiconductor Corporation at West Jordan, Utah. These structures were implemented and tested on a specially designed test chip. In addition to the typical structures of poly 1 floating gate and poly 2 control gate, new novel structures of poly 2 floating gate and poly 1 control gate were implemented. A total of five major structures are described. The author discusses the principle of operation, advantages and disadvantages of each of these structures. Also included are characteristic results and a discussion of the performance of these candidate cells |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_9d5e2a8c09d3497cc536c0334ed99964 |
| identifier_str_mv | (1992) Design, selection and implementation of flash erase EEPROM memorycells. Circuits, Devices and Systems, IEE Proceedings G, 139. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::14481 |
| publishDate | 1992 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | Design, selection and implementation of flash erase EEPROM memorycellsAmin, A.A.M.unknownComputerThe author reports an investigation into the design and process constraints of flash EEPROM memory cells. He describes several possible structures which were developed by the MOS memory RD group of National Semiconductor Corporation at West Jordan, Utah. These structures were implemented and tested on a specially designed test chip. In addition to the typical structures of poly 1 floating gate and poly 2 control gate, new novel structures of poly 2 floating gate and poly 1 control gate were implemented. A total of five major structures are described. The author discusses the principle of operation, advantages and disadvantages of each of these structures. Also included are characteristic results and a discussion of the performance of these candidate cellsIEEE1992-062020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfapplication/mswordhttps://eprints.kfupm.edu.sa/id/eprint/14481/1/14481_1.pdfhttps://eprints.kfupm.edu.sa/id/eprint/14481/2/14481_2.doc (1992) Design, selection and implementation of flash erase EEPROM memorycells. Circuits, Devices and Systems, IEE Proceedings G, 139. enenhttps://eprints.kfupm.edu.sa/id/eprint/14481/info:eu-repo/semantics/openAccessoai::144812019-11-01T14:06:00Z |
| spellingShingle | Design, selection and implementation of flash erase EEPROM memorycells Amin, A.A.M. Computer |
| status_str | publishedVersion |
| title | Design, selection and implementation of flash erase EEPROM memorycells |
| title_full | Design, selection and implementation of flash erase EEPROM memorycells |
| title_fullStr | Design, selection and implementation of flash erase EEPROM memorycells |
| title_full_unstemmed | Design, selection and implementation of flash erase EEPROM memorycells |
| title_short | Design, selection and implementation of flash erase EEPROM memorycells |
| title_sort | Design, selection and implementation of flash erase EEPROM memorycells |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/14481/1/14481_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14481/2/14481_2.doc |