VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES
A number of innovative designs have been proposed for hardware implementation of data structures. However, these designs have only been presented at an abstract behavioural level. In this paper, we describe the VLSI design and implementation of a 15-node 8-bit queue based on a systolic tree architec...
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| مؤلفون آخرون: | , |
| التنسيق: | article |
| منشور في: |
2020
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| الوصول للمادة أونلاين: | https://eprints.kfupm.edu.sa/id/eprint/292/1/VLSI_design.pdf |
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| _version_ | 1864513380275978240 |
|---|---|
| author | Sait, Sadiq M. |
| author2 | M. A. A., Khalid unknown |
| author2_role | author author |
| author_facet | Sait, Sadiq M. M. A. A., Khalid unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | Sait, Sadiq M. M. A. A., Khalid unknown |
| dc.date.*.fl_str_mv | 2020 |
| dc.format.none.fl_str_mv | application/pdf |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/292/1/VLSI_design.pdf VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES. MICROPROCESSORS AND MICROSYSTEMS 19 (3): 139-146 APR 1995. |
| dc.language.none.fl_str_mv | en |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/292/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | A number of innovative designs have been proposed for hardware implementation of data structures. However, these designs have only been presented at an abstract behavioural level. In this paper, we describe the VLSI design and implementation of a 15-node 8-bit queue based on a systolic tree architecture. A layout methodology and a VLSI CAD environment that facilitate fast and efficient layout of large binary trees are described. The objective of this paper is to illustrate the implementation of tree architectures in VLSI. We demonstrate this by implementing a systolic tree queue. Keywords: VLSI design; systolic tree architecture; automated layout |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_a87cc32df5efe863155539cdd8008d38 |
| identifier_str_mv | VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES. MICROPROCESSORS AND MICROSYSTEMS 19 (3): 139-146 APR 1995. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::292 |
| publishDate | 2020 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUESSait, Sadiq M.M. A. A., KhalidunknownComputerA number of innovative designs have been proposed for hardware implementation of data structures. However, these designs have only been presented at an abstract behavioural level. In this paper, we describe the VLSI design and implementation of a 15-node 8-bit queue based on a systolic tree architecture. A layout methodology and a VLSI CAD environment that facilitate fast and efficient layout of large binary trees are described. The objective of this paper is to illustrate the implementation of tree architectures in VLSI. We demonstrate this by implementing a systolic tree queue. Keywords: VLSI design; systolic tree architecture; automated layoutArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttps://eprints.kfupm.edu.sa/id/eprint/292/1/VLSI_design.pdf VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES. MICROPROCESSORS AND MICROSYSTEMS 19 (3): 139-146 APR 1995. enhttps://eprints.kfupm.edu.sa/id/eprint/292/2020info:eu-repo/semantics/openAccessoai::2922019-11-01T13:23:30Z |
| spellingShingle | VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES Sait, Sadiq M. Computer |
| status_str | publishedVersion |
| title | VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES |
| title_full | VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES |
| title_fullStr | VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES |
| title_full_unstemmed | VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES |
| title_short | VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES |
| title_sort | VLSI DESIGN AND IMPLEMENTATION OF SYSTOLIC TREE QUEUES |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/292/1/VLSI_design.pdf |