Performance driven standard-cell placement using the geneticalgorithm
Current placement systems attempt to optimize several objectives, namely area, connection length, and timing performance. In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm follows the genetic paradigm. Besides optimizing for area and wire length, th...
محفوظ في:
| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | , , , |
| التنسيق: | article |
| منشور في: |
1995
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| الموضوعات: | |
| الوصول للمادة أونلاين: | https://eprints.kfupm.edu.sa/id/eprint/14832/1/14832_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14832/2/14832_2.doc |
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| الملخص: | Current placement systems attempt to optimize several objectives, namely area, connection length, and timing performance. In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm follows the genetic paradigm. Besides optimizing for area and wire length, the placer minimizes the propagation delays on a predicted set of critical paths. The paths are enumerated using a new approach based on the notion of -criticality. Experiments with test circuits demonstrate delay performance improvement by up to 20% |
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