Fast elliptic curve cryptographic processor architecture based on three parallel GF(2/sup k/) bit level pipelined digit serial multipliers
Unusual processor architecture for elliptic curve encryption is proposed in this paper. The architecture exploits projective coordinates (x=X/Z, y=Y/Z) to convert GF(2/sup k/) division needed in elliptic point operations into several multiplication steps. The processor has three GF(2/sup k/) multipl...
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2003
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14101/1/14101_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14101/2/14101_2.doc |
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| _version_ | 1864513393352769536 |
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| author | Gutub, A.A.-A. |
| author2 | unknown |
| author2_role | author |
| author_facet | Gutub, A.A.-A. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | Gutub, A.A.-A. unknown |
| dc.date.none.fl_str_mv | 2003-12 2020 |
| dc.format.none.fl_str_mv | application/pdf application/msword |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14101/1/14101_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14101/2/14101_2.doc (2003) Fast elliptic curve cryptographic processor architecture based on three parallel GF(2/sup k/) bit level pipelined digit serial multipliers. Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International conference, 1. |
| dc.language.none.fl_str_mv | en en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14101/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | Fast elliptic curve cryptographic processor architecture based on three parallel GF(2/sup k/) bit level pipelined digit serial multipliers |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | Unusual processor architecture for elliptic curve encryption is proposed in this paper. The architecture exploits projective coordinates (x=X/Z, y=Y/Z) to convert GF(2/sup k/) division needed in elliptic point operations into several multiplication steps. The processor has three GF(2/sup k/) multipliers implemented using bit-level pipelined digit serial computation. It is shown that this results in a faster operation than using fully parallel multipliers with the added advantage of requiring less area. The proposed architecture is a serious contender for implementing data security systems based on elliptic curve cryptography. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_b3cb18fdab1ff15e5da082a3256dcb35 |
| identifier_str_mv | (2003) Fast elliptic curve cryptographic processor architecture based on three parallel GF(2/sup k/) bit level pipelined digit serial multipliers. Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International conference, 1. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::14101 |
| publishDate | 2003 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | Fast elliptic curve cryptographic processor architecture based on three parallel GF(2/sup k/) bit level pipelined digit serial multipliersGutub, A.A.-A.unknownComputerUnusual processor architecture for elliptic curve encryption is proposed in this paper. The architecture exploits projective coordinates (x=X/Z, y=Y/Z) to convert GF(2/sup k/) division needed in elliptic point operations into several multiplication steps. The processor has three GF(2/sup k/) multipliers implemented using bit-level pipelined digit serial computation. It is shown that this results in a faster operation than using fully parallel multipliers with the added advantage of requiring less area. The proposed architecture is a serious contender for implementing data security systems based on elliptic curve cryptography.IEEE2003-122020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfapplication/mswordhttps://eprints.kfupm.edu.sa/id/eprint/14101/1/14101_1.pdfhttps://eprints.kfupm.edu.sa/id/eprint/14101/2/14101_2.doc (2003) Fast elliptic curve cryptographic processor architecture based on three parallel GF(2/sup k/) bit level pipelined digit serial multipliers. Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International conference, 1. enenhttps://eprints.kfupm.edu.sa/id/eprint/14101/info:eu-repo/semantics/openAccessoai::141012019-11-01T14:04:10Z |
| spellingShingle | Fast elliptic curve cryptographic processor architecture based on three parallel GF(2/sup k/) bit level pipelined digit serial multipliers Gutub, A.A.-A. Computer |
| status_str | publishedVersion |
| title | Fast elliptic curve cryptographic processor architecture based on three parallel GF(2/sup k/) bit level pipelined digit serial multipliers |
| title_full | Fast elliptic curve cryptographic processor architecture based on three parallel GF(2/sup k/) bit level pipelined digit serial multipliers |
| title_fullStr | Fast elliptic curve cryptographic processor architecture based on three parallel GF(2/sup k/) bit level pipelined digit serial multipliers |
| title_full_unstemmed | Fast elliptic curve cryptographic processor architecture based on three parallel GF(2/sup k/) bit level pipelined digit serial multipliers |
| title_short | Fast elliptic curve cryptographic processor architecture based on three parallel GF(2/sup k/) bit level pipelined digit serial multipliers |
| title_sort | Fast elliptic curve cryptographic processor architecture based on three parallel GF(2/sup k/) bit level pipelined digit serial multipliers |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/14101/1/14101_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14101/2/14101_2.doc |