AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITS
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose...
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| Format: | article |
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2020
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/1644/1/P155.pdf |
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| _version_ | 1864513389905051648 |
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| author | El-Maleh, Aiman |
| author2 | Al-Suwaiyan, Ali unknown |
| author2_role | author author |
| author_facet | El-Maleh, Aiman Al-Suwaiyan, Ali unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | El-Maleh, Aiman Al-Suwaiyan, Ali unknown |
| dc.date.*.fl_str_mv | 2020 |
| dc.format.none.fl_str_mv | application/pdf |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/1644/1/P155.pdf AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITS. The 6th Saudi Engineering Conference, KFUPM, Dhahran, December 2002. |
| dc.language.none.fl_str_mv | en |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/1644/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITS |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | Reducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational circuits. It is based on critical path tracing and hence it may result in a reduction in the fault coverage. However, based on experimental results on ISCAS benchmark circuits, the drop in the fault coverage (if any) after relaxation is small for most of the circuits. The technique is faster than the brute-force test relaxation method by several orders of magnitude. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_b61960dfd9a64e808e74ae03189c1ae7 |
| identifier_str_mv | AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITS. The 6th Saudi Engineering Conference, KFUPM, Dhahran, December 2002. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::1644 |
| publishDate | 2020 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
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| spelling | AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITSEl-Maleh, AimanAl-Suwaiyan, AliunknownComputerReducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational circuits. It is based on critical path tracing and hence it may result in a reduction in the fault coverage. However, based on experimental results on ISCAS benchmark circuits, the drop in the fault coverage (if any) after relaxation is small for most of the circuits. The technique is faster than the brute-force test relaxation method by several orders of magnitude.ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttps://eprints.kfupm.edu.sa/id/eprint/1644/1/P155.pdf AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITS. The 6th Saudi Engineering Conference, KFUPM, Dhahran, December 2002. enhttps://eprints.kfupm.edu.sa/id/eprint/1644/2020info:eu-repo/semantics/openAccessoai::16442019-11-01T13:27:37Z |
| spellingShingle | AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITS El-Maleh, Aiman Computer |
| status_str | publishedVersion |
| title | AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITS |
| title_full | AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITS |
| title_fullStr | AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITS |
| title_full_unstemmed | AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITS |
| title_short | AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITS |
| title_sort | AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITS |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/1644/1/P155.pdf |