AN EFFICIENT TEST RELAXATION TECHNIQUE FOR COMBINATIONAL LOGIC CIRCUITS
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This can be achieved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of compaction and compression techniques. In this paper, we propose...
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| Format: | article |
| Published: |
2020
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/1644/1/P155.pdf |
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