An efficient test relaxation technique for combinational & full-scan sequential circuits
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper...
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2002
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/14181/1/14181_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14181/2/14181_2.doc |
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| _version_ | 1864513393389469696 |
|---|---|
| author | El-Maleh, A. |
| author2 | Al-Suwaiyan, A. unknown |
| author2_role | author author |
| author_facet | El-Maleh, A. Al-Suwaiyan, A. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | El-Maleh, A. Al-Suwaiyan, A. unknown |
| dc.date.none.fl_str_mv | 2002 2020 |
| dc.format.none.fl_str_mv | application/pdf application/msword |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14181/1/14181_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14181/2/14181_2.doc (2002) An efficient test relaxation technique for combinational & full-scan sequential circuits. VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE, 1. |
| dc.language.none.fl_str_mv | en en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/14181/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | An efficient test relaxation technique for combinational & full-scan sequential circuits |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper we propose a novel and efficient test relaxation technique for combinational and full-scan sequential circuits. The proposed technique is faster than the brute-force test relaxation method by several orders of magnitude. The application of the technique in improving the effectiveness of test compaction and compression is illustrated. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_bd3b6854ac9c60cf257a794f436f711d |
| identifier_str_mv | (2002) An efficient test relaxation technique for combinational & full-scan sequential circuits. VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE, 1. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::14181 |
| publishDate | 2002 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | An efficient test relaxation technique for combinational & full-scan sequential circuitsEl-Maleh, A.Al-Suwaiyan, A.unknownComputerReducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper we propose a novel and efficient test relaxation technique for combinational and full-scan sequential circuits. The proposed technique is faster than the brute-force test relaxation method by several orders of magnitude. The application of the technique in improving the effectiveness of test compaction and compression is illustrated.IEEE20022020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfapplication/mswordhttps://eprints.kfupm.edu.sa/id/eprint/14181/1/14181_1.pdfhttps://eprints.kfupm.edu.sa/id/eprint/14181/2/14181_2.doc (2002) An efficient test relaxation technique for combinational & full-scan sequential circuits. VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE, 1. enenhttps://eprints.kfupm.edu.sa/id/eprint/14181/info:eu-repo/semantics/openAccessoai::141812019-11-01T14:04:36Z |
| spellingShingle | An efficient test relaxation technique for combinational & full-scan sequential circuits El-Maleh, A. Computer |
| status_str | publishedVersion |
| title | An efficient test relaxation technique for combinational & full-scan sequential circuits |
| title_full | An efficient test relaxation technique for combinational & full-scan sequential circuits |
| title_fullStr | An efficient test relaxation technique for combinational & full-scan sequential circuits |
| title_full_unstemmed | An efficient test relaxation technique for combinational & full-scan sequential circuits |
| title_short | An efficient test relaxation technique for combinational & full-scan sequential circuits |
| title_sort | An efficient test relaxation technique for combinational & full-scan sequential circuits |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/14181/1/14181_1.pdf https://eprints.kfupm.edu.sa/id/eprint/14181/2/14181_2.doc |