An Efficient Test Relaxation Technique for Synchronous Sequential Circuits
Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount...
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| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | , |
| التنسيق: | article |
| منشور في: |
2003
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| الموضوعات: | |
| الوصول للمادة أونلاين: | https://eprints.kfupm.edu.sa/id/eprint/139/1/A_Static_Test_Compaction_Technique_for_Combinational_Circuits_Based_on_Independent_Fault_Clustering_icecs2003.pdf |
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| _version_ | 1864513399771103232 |
|---|---|
| author | El-Maleh, Aiman H. |
| author2 | Al-Utaibi, Khaled unknown |
| author2_role | author author |
| author_facet | El-Maleh, Aiman H. Al-Utaibi, Khaled unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | El-Maleh, Aiman H. Al-Utaibi, Khaled unknown |
| dc.date.none.fl_str_mv | 2003 2020 |
| dc.format.none.fl_str_mv | application/pdf |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/139/1/A_Static_Test_Compaction_Technique_for_Combinational_Circuits_Based_on_Independent_Fault_Clustering_icecs2003.pdf (2003) An Efficient Test Relaxation Technique for Synchronous Sequential Circuits. IEEE International Symposium on Circuits and Systems. V-545 -V-548. |
| dc.language.none.fl_str_mv | en |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/139/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | An Efficient Test Relaxation Technique for Synchronous Sequential Circuits |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. Relaxing test sequences can improve the efficiency of both test compression and test compaction. In addition, the relaxation process can identify self-initializing test sequences for synchronous sequential circuits. In this paper, we propose an efficient test relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_c2fc015510cbb63ad220f601a82e15e0 |
| identifier_str_mv | (2003) An Efficient Test Relaxation Technique for Synchronous Sequential Circuits. IEEE International Symposium on Circuits and Systems. V-545 -V-548. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::139 |
| publishDate | 2003 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | An Efficient Test Relaxation Technique for Synchronous Sequential CircuitsEl-Maleh, Aiman H.Al-Utaibi, KhaledunknownComputerTesting systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount of test data in order to reduce both the total testing time and the memory requirements for the tester. Relaxing test sequences can improve the efficiency of both test compression and test compaction. In addition, the relaxation process can identify self-initializing test sequences for synchronous sequential circuits. In this paper, we propose an efficient test relaxation technique for synchronous sequential circuits that maximizes the number of unspecified bits while maintaining the same fault coverage as the original test set.20032020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttps://eprints.kfupm.edu.sa/id/eprint/139/1/A_Static_Test_Compaction_Technique_for_Combinational_Circuits_Based_on_Independent_Fault_Clustering_icecs2003.pdf (2003) An Efficient Test Relaxation Technique for Synchronous Sequential Circuits. IEEE International Symposium on Circuits and Systems. V-545 -V-548. enhttps://eprints.kfupm.edu.sa/id/eprint/139/info:eu-repo/semantics/openAccessoai::1392019-11-01T13:22:32Z |
| spellingShingle | An Efficient Test Relaxation Technique for Synchronous Sequential Circuits El-Maleh, Aiman H. Computer |
| status_str | publishedVersion |
| title | An Efficient Test Relaxation Technique for Synchronous Sequential Circuits |
| title_full | An Efficient Test Relaxation Technique for Synchronous Sequential Circuits |
| title_fullStr | An Efficient Test Relaxation Technique for Synchronous Sequential Circuits |
| title_full_unstemmed | An Efficient Test Relaxation Technique for Synchronous Sequential Circuits |
| title_short | An Efficient Test Relaxation Technique for Synchronous Sequential Circuits |
| title_sort | An Efficient Test Relaxation Technique for Synchronous Sequential Circuits |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/139/1/A_Static_Test_Compaction_Technique_for_Combinational_Circuits_Based_on_Independent_Fault_Clustering_icecs2003.pdf |