An Efficient Test Relaxation Technique for Synchronous Sequential Circuits
Testing systems-on-a-chip (SOC) involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the circuit under test (CUT) during test application. Therefore, practical techniques, such as test compression and compaction, are required to reduce the amount...
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| Format: | article |
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2003
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/139/1/A_Static_Test_Compaction_Technique_for_Combinational_Circuits_Based_on_Independent_Fault_Clustering_icecs2003.pdf |
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