VLSI LAYOUT GENERATION OF A PROGRAMMABLE CRC CHIP
VLSI layout generation of a programable CRC chip with a CRC of 16-bits is presented. The hardware of CRC generator is specified in a hardware description language (HDL). The hardware compiler and functional level simulator of HDL are used for logic synthesis. the second stage of the compilation proc...
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| Other Authors: | , |
| Format: | article |
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2020
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/296/1/J_Sait_CE_November1993.pdf |
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