Parallelization of Iterative Heuristic for Performance-Driven Low-Power VLSI Standard Cell Placement.
The complexity involved in VLSI design and its sub-problems has always made them ideal application areas for non-deterministic iterative heuristics. However, the major drawback has been the large runtime involved in reaching acceptable solutions especially in the case of multi-objective optimization...
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| Format: | masterThesis |
| Published: |
2003
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/59/1/Sanaullah.Syed.Thesis.Nov.2003.pdf |
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