Interconnect-Efficient LDPC Code Design
In this paper, we present a new, hardware-oriented technique for designing Low Density Parity Check (LDPC) codes. The technique targets to achieve an interconnect-efficient architecture that reduces the area and delay of the decoder implementation while maintaining good error correction performance....
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| Format: | article |
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2006
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| Online Access: | https://eprints.kfupm.edu.sa/id/eprint/162/1/Interconnect-Efficient_LDPC_Code_Design_ICM2006.pdf |
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| _version_ | 1864513379777904640 |
|---|---|
| author | El-Maleh, Aiman H. |
| author2 | Arkasosy, Basil Andalusi, Adnan unknown |
| author2_role | author author author |
| author_facet | El-Maleh, Aiman H. Arkasosy, Basil Andalusi, Adnan unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | El-Maleh, Aiman H. Arkasosy, Basil Andalusi, Adnan unknown |
| dc.date.none.fl_str_mv | 2006-12 2020 |
| dc.format.none.fl_str_mv | application/pdf |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/162/1/Interconnect-Efficient_LDPC_Code_Design_ICM2006.pdf (2006) Interconnect-Efficient LDPC Code Design. 18th IEEE Int. Conf. on Microlelectronics. pp. 127-130. |
| dc.language.none.fl_str_mv | en |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/162/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer Electrical |
| dc.title.none.fl_str_mv | Interconnect-Efficient LDPC Code Design |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | In this paper, we present a new, hardware-oriented technique for designing Low Density Parity Check (LDPC) codes. The technique targets to achieve an interconnect-efficient architecture that reduces the area and delay of the decoder implementation while maintaining good error correction performance. With a fully parallel implementation of the LDPC decoder, the proposed design assumes a constraint on the interconnect wire length which has a direct impact on the maximum signal delay and power dissipation. Furthermore, this design approach is shown to lower interconnect routing congestion, and hence reduce the chip area and maximize chip utilization. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_de3e92cdd759c725aca2361bca6244b7 |
| identifier_str_mv | (2006) Interconnect-Efficient LDPC Code Design. 18th IEEE Int. Conf. on Microlelectronics. pp. 127-130. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::162 |
| publishDate | 2006 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | Interconnect-Efficient LDPC Code DesignEl-Maleh, Aiman H.Arkasosy, BasilAndalusi, AdnanunknownComputerElectricalIn this paper, we present a new, hardware-oriented technique for designing Low Density Parity Check (LDPC) codes. The technique targets to achieve an interconnect-efficient architecture that reduces the area and delay of the decoder implementation while maintaining good error correction performance. With a fully parallel implementation of the LDPC decoder, the proposed design assumes a constraint on the interconnect wire length which has a direct impact on the maximum signal delay and power dissipation. Furthermore, this design approach is shown to lower interconnect routing congestion, and hence reduce the chip area and maximize chip utilization.2006-122020ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttps://eprints.kfupm.edu.sa/id/eprint/162/1/Interconnect-Efficient_LDPC_Code_Design_ICM2006.pdf (2006) Interconnect-Efficient LDPC Code Design. 18th IEEE Int. Conf. on Microlelectronics. pp. 127-130. enhttps://eprints.kfupm.edu.sa/id/eprint/162/info:eu-repo/semantics/openAccessoai::1622019-11-01T13:22:41Z |
| spellingShingle | Interconnect-Efficient LDPC Code Design El-Maleh, Aiman H. Computer Electrical |
| status_str | publishedVersion |
| title | Interconnect-Efficient LDPC Code Design |
| title_full | Interconnect-Efficient LDPC Code Design |
| title_fullStr | Interconnect-Efficient LDPC Code Design |
| title_full_unstemmed | Interconnect-Efficient LDPC Code Design |
| title_short | Interconnect-Efficient LDPC Code Design |
| title_sort | Interconnect-Efficient LDPC Code Design |
| topic | Computer Electrical |
| url | https://eprints.kfupm.edu.sa/id/eprint/162/1/Interconnect-Efficient_LDPC_Code_Design_ICM2006.pdf |