A novel technique for fast multiplication
In this paper we present the design of a new high-speed multiplication unit. The design is based on non-overlapped scanning of 3-bit ® elds of the multiplier. In this technique the partial products of the multiplicand and three bits of the multiplier are pre-calculated using only hardwired shifts. T...
محفوظ في:
| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | , , |
| التنسيق: | article |
| منشور في: |
2020
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| الموضوعات: | |
| الوصول للمادة أونلاين: | https://eprints.kfupm.edu.sa/id/eprint/283/1/J_Sait_IJE_January1999.pdf |
| الوسوم: |
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| الملخص: | In this paper we present the design of a new high-speed multiplication unit. The design is based on non-overlapped scanning of 3-bit ® elds of the multiplier. In this technique the partial products of the multiplicand and three bits of the multiplier are pre-calculated using only hardwired shifts. These partial products are then added using a tree of carry-save-adders, and ® nally the sum and carry vectors are added using a carry-lookahead adder. In the case of 2 s complement multiplication the tree of carry-save-adders also receives a correction output produced in parallel with the partial products. The algorithm is modelled in a hardware description language and its VLSI chip implemented. The performance of the new design is comparedwith that of other recent ones proposed in literature. |
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