A novel technique for fast multiplication
In this paper we present the design of a new high-speed multiplication unit. The design is based on non-overlapped scanning of 3-bit ® elds of the multiplier. In this technique the partial products of the multiplicand and three bits of the multiplier are pre-calculated using only hardwired shifts. T...
محفوظ في:
| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | , , |
| التنسيق: | article |
| منشور في: |
2020
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| الموضوعات: | |
| الوصول للمادة أونلاين: | https://eprints.kfupm.edu.sa/id/eprint/283/1/J_Sait_IJE_January1999.pdf |
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| _version_ | 1864513399785783296 |
|---|---|
| author | Sait, Sadiq M. |
| author2 | Farooqui, Aamir A. Beckhoff, G. F. unknown |
| author2_role | author author author |
| author_facet | Sait, Sadiq M. Farooqui, Aamir A. Beckhoff, G. F. unknown |
| author_role | author |
| dc.creator.none.fl_str_mv | Sait, Sadiq M. Farooqui, Aamir A. Beckhoff, G. F. unknown |
| dc.date.*.fl_str_mv | 2020 |
| dc.format.none.fl_str_mv | application/pdf |
| dc.identifier.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/283/1/J_Sait_IJE_January1999.pdf A novel technique for fast multiplication. INTERNATIONAL JOURNAL OF ELECTRONICS 86 (1): 67-77 JAN 1999. |
| dc.language.none.fl_str_mv | en |
| dc.relation.none.fl_str_mv | https://eprints.kfupm.edu.sa/id/eprint/283/ |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.subject.none.fl_str_mv | Computer |
| dc.title.none.fl_str_mv | A novel technique for fast multiplication |
| dc.type.none.fl_str_mv | Article PeerReviewed info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | In this paper we present the design of a new high-speed multiplication unit. The design is based on non-overlapped scanning of 3-bit ® elds of the multiplier. In this technique the partial products of the multiplicand and three bits of the multiplier are pre-calculated using only hardwired shifts. These partial products are then added using a tree of carry-save-adders, and ® nally the sum and carry vectors are added using a carry-lookahead adder. In the case of 2 s complement multiplication the tree of carry-save-adders also receives a correction output produced in parallel with the partial products. The algorithm is modelled in a hardware description language and its VLSI chip implemented. The performance of the new design is comparedwith that of other recent ones proposed in literature. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | KFUPM_f02eab8d25a5bb5be18d3e31b8467124 |
| identifier_str_mv | A novel technique for fast multiplication. INTERNATIONAL JOURNAL OF ELECTRONICS 86 (1): 67-77 JAN 1999. |
| language_invalid_str_mv | en |
| network_acronym_str | KFUPM |
| network_name_str | King Fahd University of Petroleum and Minerals |
| oai_identifier_str | oai::283 |
| publishDate | 2020 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | A novel technique for fast multiplicationSait, Sadiq M.Farooqui, Aamir A.Beckhoff, G. F.unknownComputerIn this paper we present the design of a new high-speed multiplication unit. The design is based on non-overlapped scanning of 3-bit ® elds of the multiplier. In this technique the partial products of the multiplicand and three bits of the multiplier are pre-calculated using only hardwired shifts. These partial products are then added using a tree of carry-save-adders, and ® nally the sum and carry vectors are added using a carry-lookahead adder. In the case of 2 s complement multiplication the tree of carry-save-adders also receives a correction output produced in parallel with the partial products. The algorithm is modelled in a hardware description language and its VLSI chip implemented. The performance of the new design is comparedwith that of other recent ones proposed in literature.ArticlePeerReviewedinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/articleapplication/pdfhttps://eprints.kfupm.edu.sa/id/eprint/283/1/J_Sait_IJE_January1999.pdf A novel technique for fast multiplication. INTERNATIONAL JOURNAL OF ELECTRONICS 86 (1): 67-77 JAN 1999. enhttps://eprints.kfupm.edu.sa/id/eprint/283/2020info:eu-repo/semantics/openAccessoai::2832019-11-01T13:23:27Z |
| spellingShingle | A novel technique for fast multiplication Sait, Sadiq M. Computer |
| status_str | publishedVersion |
| title | A novel technique for fast multiplication |
| title_full | A novel technique for fast multiplication |
| title_fullStr | A novel technique for fast multiplication |
| title_full_unstemmed | A novel technique for fast multiplication |
| title_short | A novel technique for fast multiplication |
| title_sort | A novel technique for fast multiplication |
| topic | Computer |
| url | https://eprints.kfupm.edu.sa/id/eprint/283/1/J_Sait_IJE_January1999.pdf |