A method for efficient NoC test scheduling using deterministic routing
Network-on-Chip (NoC) is an on-chip communication methodology that has been proposed as an alternative to bus-based communication in order to cope with the increased complexity in embedded designs. This paper presents a method for NoCs test scheduling using simulated annealing. The method uses a det...
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| Main Author: | Harmanani, Haidar (author) |
|---|---|
| Other Authors: | Farah, Rana (author) |
| Format: | conferenceObject |
| Published: |
2017
|
| Online Access: | http://hdl.handle.net/10725/5451 http://dx.doi.org/10.1109/SOCC.2010.5784696 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/5784696/ |
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