Global memory mapping for FPGA-based reconfigurable systems
Synthesizing designs for FPGA-based reconfigurable systems involves the task of mapping variables and data structures of the application onto RAMs of the reconfigurable board. The variety in types and performance of onboard and on-chip RAMs, their proximity to the processing units, and the interconn...
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2001
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| Online Access: | http://hdl.handle.net/10725/6692 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php https://www.researchgate.net/profile/Iyad_Ouaiss/publication/220950099_Global_memory_mapping_for_FPGA-based_reconfigurable_systems/links/0046352ee00bea81db000000.pdf |
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| _version_ | 1864513480616312832 |
|---|---|
| author | Ouaiss, Iyad |
| author2 | Vemiri, Ranga |
| author2_role | author |
| author_facet | Ouaiss, Iyad Vemiri, Ranga |
| author_role | author |
| dc.creator.none.fl_str_mv | Ouaiss, Iyad Vemiri, Ranga |
| dc.date.none.fl_str_mv | 2001 2017-12-01T12:03:38Z 2017-12-01T12:03:38Z 2017-12-01 |
| dc.identifier.none.fl_str_mv | http://hdl.handle.net/10725/6692 Ouaiss, I., & Vemuri, R. (2001, April). Global memory mapping for FPGA-based reconfigurable systems. In null (p. 30144b). IEEE. http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php https://www.researchgate.net/profile/Iyad_Ouaiss/publication/220950099_Global_memory_mapping_for_FPGA-based_reconfigurable_systems/links/0046352ee00bea81db000000.pdf |
| dc.language.none.fl_str_mv | en |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.title.none.fl_str_mv | Global memory mapping for FPGA-based reconfigurable systems |
| dc.type.none.fl_str_mv | Conference Paper / Proceeding info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/conferenceObject |
| description | Synthesizing designs for FPGA-based reconfigurable systems involves the task of mapping variables and data structures of the application onto RAMs of the reconfigurable board. The variety in types and performance of onboard and on-chip RAMs, their proximity to the processing units, and the interconnection scheme of the reconfigurable system, all contribute to an intricate memory mapping problem. An intelligent memory assignment minimizes the total latency of the design and the interconnection requirements due to memory accesses. A complete Integer Linear Programming (ILP) formulation of the problem results in an optimized memory mapping; however, the formulation is complex and takes a very long time to produce a solution. In order to efficiently solve the problem, the concept of global/detailed memory mapping is introduced in this paper. An ILP formulation of the global mapping process is described. This formulation is simpler and faster than the complete formulation, and it leaves the task of detailed mapping to a post-ILP tool that does not affect the optimality of the memory assignment. As a result, larger designs can be handled at a faster rate and more constraints can be introduced to the formulation |
| eu_rights_str_mv | openAccess |
| format | conferenceObject |
| id | LAURepo_2acf7828d495c6e72eae209c77fc003a |
| identifier_str_mv | Ouaiss, I., & Vemuri, R. (2001, April). Global memory mapping for FPGA-based reconfigurable systems. In null (p. 30144b). IEEE. |
| language_invalid_str_mv | en |
| network_acronym_str | LAURepo |
| network_name_str | Lebanese American University repository |
| oai_identifier_str | oai:laur.lau.edu.lb:10725/6692 |
| publishDate | 2001 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | Global memory mapping for FPGA-based reconfigurable systemsOuaiss, IyadVemiri, RangaSynthesizing designs for FPGA-based reconfigurable systems involves the task of mapping variables and data structures of the application onto RAMs of the reconfigurable board. The variety in types and performance of onboard and on-chip RAMs, their proximity to the processing units, and the interconnection scheme of the reconfigurable system, all contribute to an intricate memory mapping problem. An intelligent memory assignment minimizes the total latency of the design and the interconnection requirements due to memory accesses. A complete Integer Linear Programming (ILP) formulation of the problem results in an optimized memory mapping; however, the formulation is complex and takes a very long time to produce a solution. In order to efficiently solve the problem, the concept of global/detailed memory mapping is introduced in this paper. An ILP formulation of the global mapping process is described. This formulation is simpler and faster than the complete formulation, and it leaves the task of detailed mapping to a post-ILP tool that does not affect the optimality of the memory assignment. As a result, larger designs can be handled at a faster rate and more constraints can be introduced to the formulationN/A2017-12-01T12:03:38Z2017-12-01T12:03:38Z20012017-12-01Conference Paper / Proceedinginfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObjecthttp://hdl.handle.net/10725/6692Ouaiss, I., & Vemuri, R. (2001, April). Global memory mapping for FPGA-based reconfigurable systems. In null (p. 30144b). IEEE.http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.phphttps://www.researchgate.net/profile/Iyad_Ouaiss/publication/220950099_Global_memory_mapping_for_FPGA-based_reconfigurable_systems/links/0046352ee00bea81db000000.pdfeninfo:eu-repo/semantics/openAccessoai:laur.lau.edu.lb:10725/66922021-03-19T10:03:29Z |
| spellingShingle | Global memory mapping for FPGA-based reconfigurable systems Ouaiss, Iyad |
| status_str | publishedVersion |
| title | Global memory mapping for FPGA-based reconfigurable systems |
| title_full | Global memory mapping for FPGA-based reconfigurable systems |
| title_fullStr | Global memory mapping for FPGA-based reconfigurable systems |
| title_full_unstemmed | Global memory mapping for FPGA-based reconfigurable systems |
| title_short | Global memory mapping for FPGA-based reconfigurable systems |
| title_sort | Global memory mapping for FPGA-based reconfigurable systems |
| url | http://hdl.handle.net/10725/6692 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php https://www.researchgate.net/profile/Iyad_Ouaiss/publication/220950099_Global_memory_mapping_for_FPGA-based_reconfigurable_systems/links/0046352ee00bea81db000000.pdf |