SYNTEST
The article introduces a new high-level synthesis method for self-testable RTL designs. A basic feature of this method is a structural testability model which treats testability as a structural design style integrated in the design process. The main objective is to develop a system-level synthesis t...
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| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | , |
| التنسيق: | conferenceObject |
| منشور في: |
2017
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| الوصول للمادة أونلاين: | http://hdl.handle.net/10725/5466 http://dx.doi.org/10.1109/ICCD.1991.139947 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/139947/ |
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| _version_ | 1864513477080514560 |
|---|---|
| author | Harmanani, H. |
| author2 | Papchristou, C. Chiu, S. |
| author2_role | author author |
| author_facet | Harmanani, H. Papchristou, C. Chiu, S. |
| author_role | author |
| dc.creator.none.fl_str_mv | Harmanani, H. Papchristou, C. Chiu, S. |
| dc.date.none.fl_str_mv | 2017-03-30T10:57:15Z 2017-03-30T10:57:15Z 2017-03-30 |
| dc.identifier.none.fl_str_mv | 0-8186-2270-9 http://hdl.handle.net/10725/5466 http://dx.doi.org/10.1109/ICCD.1991.139947 Papachristou, C., Chiu, S., & Harmanani, H. (1991, October). SYNTEST: a method for high-level SYNthesis with self-TESTability. In Computer Design: VLSI in Computers and Processors, 1991. ICCD'91. Proceedings, 1991 IEEE International Conference on (pp. 458-462). IEEE. http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/139947/ |
| dc.language.none.fl_str_mv | en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.title.none.fl_str_mv | SYNTEST a method for high-level SYNthesis with self-TESTability |
| dc.type.none.fl_str_mv | Conference Paper / Proceeding info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/conferenceObject |
| description | The article introduces a new high-level synthesis method for self-testable RTL designs. A basic feature of this method is a structural testability model which treats testability as a structural design style integrated in the design process. The main objective is to develop a system-level synthesis tool set mapping a behavioral description onto an optimized and testable RTL design subject to user-defined constraints. The approach involves several major components within the following system-level iteration: scheduling and allocation, constraint estimation, and testability tradeoffs. |
| eu_rights_str_mv | openAccess |
| format | conferenceObject |
| id | LAURepo_54f2d21bc5fb38e9ba401f0866c0153d |
| identifier_str_mv | 0-8186-2270-9 Papachristou, C., Chiu, S., & Harmanani, H. (1991, October). SYNTEST: a method for high-level SYNthesis with self-TESTability. In Computer Design: VLSI in Computers and Processors, 1991. ICCD'91. Proceedings, 1991 IEEE International Conference on (pp. 458-462). IEEE. |
| language_invalid_str_mv | en |
| network_acronym_str | LAURepo |
| network_name_str | Lebanese American University repository |
| oai_identifier_str | oai:laur.lau.edu.lb:10725/5466 |
| publishDate | 2017 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | SYNTESTa method for high-level SYNthesis with self-TESTabilityHarmanani, H.Papchristou, C.Chiu, S.The article introduces a new high-level synthesis method for self-testable RTL designs. A basic feature of this method is a structural testability model which treats testability as a structural design style integrated in the design process. The main objective is to develop a system-level synthesis tool set mapping a behavioral description onto an optimized and testable RTL design subject to user-defined constraints. The approach involves several major components within the following system-level iteration: scheduling and allocation, constraint estimation, and testability tradeoffs.N/AIEEE2017-03-30T10:57:15Z2017-03-30T10:57:15Z2017-03-30Conference Paper / Proceedinginfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject0-8186-2270-9http://hdl.handle.net/10725/5466http://dx.doi.org/10.1109/ICCD.1991.139947Papachristou, C., Chiu, S., & Harmanani, H. (1991, October). SYNTEST: a method for high-level SYNthesis with self-TESTability. In Computer Design: VLSI in Computers and Processors, 1991. ICCD'91. Proceedings, 1991 IEEE International Conference on (pp. 458-462). IEEE.http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.phphttp://ieeexplore.ieee.org/abstract/document/139947/eninfo:eu-repo/semantics/openAccessoai:laur.lau.edu.lb:10725/54662021-03-19T10:00:56Z |
| spellingShingle | SYNTEST Harmanani, H. |
| status_str | publishedVersion |
| title | SYNTEST |
| title_full | SYNTEST |
| title_fullStr | SYNTEST |
| title_full_unstemmed | SYNTEST |
| title_short | SYNTEST |
| title_sort | SYNTEST |
| url | http://hdl.handle.net/10725/5466 http://dx.doi.org/10.1109/ICCD.1991.139947 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/139947/ |