Test bus assignment, sizing, and partitioning for system-on-chip
The test access mechanism (TAM) is an important element of test architectures for embedded cores and is responsible for on-chip test pattern transport from the source to the core under test to the sink. Efficient TAM design is of critical importance in system-on-chip integration since it directly im...
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| Format: | article |
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2007
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| Online Access: | http://hdl.handle.net/10725/3528 http://dx.doi.org/10.1109/CJECE.2007.4413128 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4413128 |
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| _version_ | 1864513461374943232 |
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| author | Harmanani, Haidar M. |
| author2 | Sawan, Rachel |
| author2_role | author |
| author_facet | Harmanani, Haidar M. Sawan, Rachel |
| author_role | author |
| dc.creator.none.fl_str_mv | Harmanani, Haidar M. Sawan, Rachel |
| dc.date.none.fl_str_mv | 2007 2016-04-11T12:37:51Z 2016-04-11T12:37:51Z 2017-08-10 |
| dc.identifier.none.fl_str_mv | 0840-8688 http://hdl.handle.net/10725/3528 http://dx.doi.org/10.1109/CJECE.2007.4413128 Harmanani, H. M., & Sawan, R. (2007). Test bus assignment, sizing, and partitioning for system-on-chip. Electrical and Computer Engineering, Canadian Journal of, 32(3), 165-175. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4413128 |
| dc.language.none.fl_str_mv | en |
| dc.relation.none.fl_str_mv | Canadian Journal of Electrical and Computer Engineering |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.title.none.fl_str_mv | Test bus assignment, sizing, and partitioning for system-on-chip |
| dc.type.none.fl_str_mv | Article info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/article |
| description | The test access mechanism (TAM) is an important element of test architectures for embedded cores and is responsible for on-chip test pattern transport from the source to the core under test to the sink. Efficient TAM design is of critical importance in system-on-chip integration since it directly impacts testing time and hardware cost. In this paper, an efficient genetic algorithm for designing test access architectures while investigating test bus sizing and concurrently assigning cores to test buses is proposed. Experimental results are presented to demonstrate that the proposed TAM optimization methodology provides efficient test bus designs with minimum testing time while outperforming reported techniques. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | LAURepo_6b2ee3a5f9fd15dd8fbd5b5c80ff607d |
| identifier_str_mv | 0840-8688 Harmanani, H. M., & Sawan, R. (2007). Test bus assignment, sizing, and partitioning for system-on-chip. Electrical and Computer Engineering, Canadian Journal of, 32(3), 165-175. |
| language_invalid_str_mv | en |
| network_acronym_str | LAURepo |
| network_name_str | Lebanese American University repository |
| oai_identifier_str | oai:laur.lau.edu.lb:10725/3528 |
| publishDate | 2007 |
| repository.mail.fl_str_mv | |
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| spelling | Test bus assignment, sizing, and partitioning for system-on-chipHarmanani, Haidar M.Sawan, RachelThe test access mechanism (TAM) is an important element of test architectures for embedded cores and is responsible for on-chip test pattern transport from the source to the core under test to the sink. Efficient TAM design is of critical importance in system-on-chip integration since it directly impacts testing time and hardware cost. In this paper, an efficient genetic algorithm for designing test access architectures while investigating test bus sizing and concurrently assigning cores to test buses is proposed. Experimental results are presented to demonstrate that the proposed TAM optimization methodology provides efficient test bus designs with minimum testing time while outperforming reported techniques.PublishedN/A2016-04-11T12:37:51Z2016-04-11T12:37:51Z20072017-08-10Articleinfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/article0840-8688http://hdl.handle.net/10725/3528http://dx.doi.org/10.1109/CJECE.2007.4413128Harmanani, H. M., & Sawan, R. (2007). Test bus assignment, sizing, and partitioning for system-on-chip. Electrical and Computer Engineering, Canadian Journal of, 32(3), 165-175.http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4413128enCanadian Journal of Electrical and Computer Engineeringinfo:eu-repo/semantics/openAccessoai:laur.lau.edu.lb:10725/35282021-03-19T10:00:46Z |
| spellingShingle | Test bus assignment, sizing, and partitioning for system-on-chip Harmanani, Haidar M. |
| status_str | publishedVersion |
| title | Test bus assignment, sizing, and partitioning for system-on-chip |
| title_full | Test bus assignment, sizing, and partitioning for system-on-chip |
| title_fullStr | Test bus assignment, sizing, and partitioning for system-on-chip |
| title_full_unstemmed | Test bus assignment, sizing, and partitioning for system-on-chip |
| title_short | Test bus assignment, sizing, and partitioning for system-on-chip |
| title_sort | Test bus assignment, sizing, and partitioning for system-on-chip |
| url | http://hdl.handle.net/10725/3528 http://dx.doi.org/10.1109/CJECE.2007.4413128 http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4413128 |