Resource allocation and reallocation techniques in high-level synthesis with testability constraint
The increase in density that the advent of Very Large Scale Integration (VLSI) has allowed, made the move to higher levels of design abstraction imperative. High Level Synthesis emerged as a result; however, most solutions (1) were not optimal; (2) did not incorporate testing at the system level. In...
محفوظ في:
| المؤلف الرئيسي: | Harmanani, Haidar M. (author) |
|---|---|
| التنسيق: | masterThesis |
| منشور في: |
1994
|
| الوصول للمادة أونلاين: | http://hdl.handle.net/10725/7647 http://libraries.lau.edu.lb/research/laur/terms-of-use/thesis.php https://etd.ohiolink.edu/pg_10?0::NO:10:P10_ACCESSION_NUM:case1057758522 |
| الوسوم: |
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مواد مشابهة
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Testable data path synthesis with integer linear programming allocation
حسب: Harmanani, H.M.
منشور في: (1991) -
An Evolutionary Algorithm for the Allocation Problem in High-Level Synthesis
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منشور في: (2005) -
Distributed control in testable high-level synthesis with low area and power overhead
حسب: Harmanani, Harmanani
منشور في: (2017) -
An improved method for RTL synthesis with testability tradeoffs
حسب: Harmanani, Haidar
منشور في: (2017) -
An approach for redesign for testability at the register-transfer level
حسب: Harmanani, Haidar M.
منشور في: (2000)