A method for redesign for testability at the RT level
A new method of redesign for testability at the register-transfer level (RTL) is proposed. The method identifies hard to test parts of a an RTL design synthesized either manually or automatically using high-level synthesis tools. The design is modified by inserting additional test registers followed...
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| المؤلف الرئيسي: | |
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| مؤلفون آخرون: | |
| التنسيق: | conferenceObject |
| منشور في: |
2017
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| الوصول للمادة أونلاين: | http://hdl.handle.net/10725/5465 http://dx.doi.org/10.1109/CCECE.1998.682706 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/682706/ |
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| _version_ | 1864513477079465984 |
|---|---|
| author | Harmanani, H. |
| author2 | Harfoush, S. |
| author2_role | author |
| author_facet | Harmanani, H. Harfoush, S. |
| author_role | author |
| dc.creator.none.fl_str_mv | Harmanani, H. Harfoush, S. |
| dc.date.none.fl_str_mv | 2017-03-30T10:35:20Z 2017-03-30T10:35:20Z 2017-03-30 |
| dc.identifier.none.fl_str_mv | 0-7803-4314-X http://hdl.handle.net/10725/5465 http://dx.doi.org/10.1109/CCECE.1998.682706 Harmanani, H., & Harfoush, S. (1998, May). A method for redesign for testability at the RT level. In Electrical and Computer Engineering, 1998. IEEE Canadian Conference on (Vol. 1, pp. 157-160). IEEE. http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/682706/ |
| dc.language.none.fl_str_mv | en |
| dc.publisher.none.fl_str_mv | IEEE |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.title.none.fl_str_mv | A method for redesign for testability at the RT level |
| dc.type.none.fl_str_mv | Conference Paper / Proceeding info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/conferenceObject |
| description | A new method of redesign for testability at the register-transfer level (RTL) is proposed. The method identifies hard to test parts of a an RTL design synthesized either manually or automatically using high-level synthesis tools. The design is modified by inserting additional test registers followed by a test selection process. During the selection process, two test metrics are used in order to minimize test overhead. Finally, test scheduling is performed so that to minimize the overall test time and the number of test sessions. The system outputs a VHDL description of a testable data path along with a test plan. |
| eu_rights_str_mv | openAccess |
| format | conferenceObject |
| id | LAURepo_838f5fffd5cdd9d6dc245f6c2490a34d |
| identifier_str_mv | 0-7803-4314-X Harmanani, H., & Harfoush, S. (1998, May). A method for redesign for testability at the RT level. In Electrical and Computer Engineering, 1998. IEEE Canadian Conference on (Vol. 1, pp. 157-160). IEEE. |
| language_invalid_str_mv | en |
| network_acronym_str | LAURepo |
| network_name_str | Lebanese American University repository |
| oai_identifier_str | oai:laur.lau.edu.lb:10725/5465 |
| publishDate | 2017 |
| publisher.none.fl_str_mv | IEEE |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | A method for redesign for testability at the RT levelHarmanani, H.Harfoush, S.A new method of redesign for testability at the register-transfer level (RTL) is proposed. The method identifies hard to test parts of a an RTL design synthesized either manually or automatically using high-level synthesis tools. The design is modified by inserting additional test registers followed by a test selection process. During the selection process, two test metrics are used in order to minimize test overhead. Finally, test scheduling is performed so that to minimize the overall test time and the number of test sessions. The system outputs a VHDL description of a testable data path along with a test plan.N/AIEEE2017-03-30T10:35:20Z2017-03-30T10:35:20Z2017-03-30Conference Paper / Proceedinginfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObject0-7803-4314-Xhttp://hdl.handle.net/10725/5465http://dx.doi.org/10.1109/CCECE.1998.682706Harmanani, H., & Harfoush, S. (1998, May). A method for redesign for testability at the RT level. In Electrical and Computer Engineering, 1998. IEEE Canadian Conference on (Vol. 1, pp. 157-160). IEEE.http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.phphttp://ieeexplore.ieee.org/abstract/document/682706/eninfo:eu-repo/semantics/openAccessoai:laur.lau.edu.lb:10725/54652021-03-19T10:00:48Z |
| spellingShingle | A method for redesign for testability at the RT level Harmanani, H. |
| status_str | publishedVersion |
| title | A method for redesign for testability at the RT level |
| title_full | A method for redesign for testability at the RT level |
| title_fullStr | A method for redesign for testability at the RT level |
| title_full_unstemmed | A method for redesign for testability at the RT level |
| title_short | A method for redesign for testability at the RT level |
| title_sort | A method for redesign for testability at the RT level |
| url | http://hdl.handle.net/10725/5465 http://dx.doi.org/10.1109/CCECE.1998.682706 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php http://ieeexplore.ieee.org/abstract/document/682706/ |