A unified specification model of concurrency and coordination for synthesis from VHDL
This paper proposes a Unified Specification Model (USM) of concurrency and coordination compatible with VHDL. The specification model embodies a uniform treatment of computation, communication channels, and memories, facilitating its use across a variety of synthesis applications. We briefly discuss...
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2017
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| Online Access: | http://hdl.handle.net/10725/5815 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php https://scholar.google.com/scholar?hl=en&q=A+unified+specification+model+of+concurrency+and+coordination+for+synthesis+from+VHDL&btnG=&as_sdt=1%2C5&as_sdtp= |
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| _version_ | 1864513477877432320 |
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| author | Ouaiss, Iyad |
| author2 | Govindarajan, Sriram Srinivasan, Vinoo Kaul, Meenakshi Vemuri, Ranga |
| author2_role | author author author author |
| author_facet | Ouaiss, Iyad Govindarajan, Sriram Srinivasan, Vinoo Kaul, Meenakshi Vemuri, Ranga |
| author_role | author |
| dc.creator.none.fl_str_mv | Ouaiss, Iyad Govindarajan, Sriram Srinivasan, Vinoo Kaul, Meenakshi Vemuri, Ranga |
| dc.date.none.fl_str_mv | 2017-06-22T11:02:57Z 2017-06-22T11:02:57Z 2017-06-22 |
| dc.identifier.none.fl_str_mv | http://hdl.handle.net/10725/5815 Ouaiss, I., Govindarajan, S., Srinivasan, V., Kaul, M., & Vemuri, R. (1998, July). A unified specification model of concurrency and coordination for synthesis from VHDL. In Proceedings of the 4th International Conference on Information Systems Analysis and Synthesis (pp. 771-778). http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php https://scholar.google.com/scholar?hl=en&q=A+unified+specification+model+of+concurrency+and+coordination+for+synthesis+from+VHDL&btnG=&as_sdt=1%2C5&as_sdtp= |
| dc.language.none.fl_str_mv | en |
| dc.rights.*.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.title.none.fl_str_mv | A unified specification model of concurrency and coordination for synthesis from VHDL |
| dc.type.none.fl_str_mv | Conference Paper / Proceeding info:eu-repo/semantics/publishedVersion info:eu-repo/semantics/conferenceObject |
| description | This paper proposes a Unified Specification Model (USM) of concurrency and coordination compatible with VHDL. The specification model embodies a uniform treatment of computation, communication channels, and memories, facilitating its use across a variety of synthesis applications. We briefly discuss synthesis semantics of the USM representation and its use in behavioral VLSI synthesis, co-synthesis, and adaptive system synthesis. We also discuss the advantages of the synchronization model in USM in comparison to similar VHDL motivated representations. Keywords: Input Specification Model, Behavioral HighLevel Synthesis, Hardware/Software Co-synthesis, Adaptive System Synthesis, and VHDL. 1. INTRODUCTION VHDL has been used for behavior level specifications for a variety of high-level synthesis tools, hardwaresoftware co-synthesis systems, and adaptive system synthesis environments. VHDL provides a rich set of high-level constructs to permit succinct specification of concurrent and coor... |
| eu_rights_str_mv | openAccess |
| format | conferenceObject |
| id | LAURepo_88b3bf146b35988fefa1940496645d6d |
| identifier_str_mv | Ouaiss, I., Govindarajan, S., Srinivasan, V., Kaul, M., & Vemuri, R. (1998, July). A unified specification model of concurrency and coordination for synthesis from VHDL. In Proceedings of the 4th International Conference on Information Systems Analysis and Synthesis (pp. 771-778). |
| language_invalid_str_mv | en |
| network_acronym_str | LAURepo |
| network_name_str | Lebanese American University repository |
| oai_identifier_str | oai:laur.lau.edu.lb:10725/5815 |
| publishDate | 2017 |
| repository.mail.fl_str_mv | |
| repository.name.fl_str_mv | |
| repository_id_str | |
| spelling | A unified specification model of concurrency and coordination for synthesis from VHDLOuaiss, IyadGovindarajan, SriramSrinivasan, VinooKaul, MeenakshiVemuri, RangaThis paper proposes a Unified Specification Model (USM) of concurrency and coordination compatible with VHDL. The specification model embodies a uniform treatment of computation, communication channels, and memories, facilitating its use across a variety of synthesis applications. We briefly discuss synthesis semantics of the USM representation and its use in behavioral VLSI synthesis, co-synthesis, and adaptive system synthesis. We also discuss the advantages of the synchronization model in USM in comparison to similar VHDL motivated representations. Keywords: Input Specification Model, Behavioral HighLevel Synthesis, Hardware/Software Co-synthesis, Adaptive System Synthesis, and VHDL. 1. INTRODUCTION VHDL has been used for behavior level specifications for a variety of high-level synthesis tools, hardwaresoftware co-synthesis systems, and adaptive system synthesis environments. VHDL provides a rich set of high-level constructs to permit succinct specification of concurrent and coor...N/A2017-06-22T11:02:57Z2017-06-22T11:02:57Z2017-06-22Conference Paper / Proceedinginfo:eu-repo/semantics/publishedVersioninfo:eu-repo/semantics/conferenceObjecthttp://hdl.handle.net/10725/5815Ouaiss, I., Govindarajan, S., Srinivasan, V., Kaul, M., & Vemuri, R. (1998, July). A unified specification model of concurrency and coordination for synthesis from VHDL. In Proceedings of the 4th International Conference on Information Systems Analysis and Synthesis (pp. 771-778).http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.phphttps://scholar.google.com/scholar?hl=en&q=A+unified+specification+model+of+concurrency+and+coordination+for+synthesis+from+VHDL&btnG=&as_sdt=1%2C5&as_sdtp=eninfo:eu-repo/semantics/openAccessoai:laur.lau.edu.lb:10725/58152021-03-19T10:03:25Z |
| spellingShingle | A unified specification model of concurrency and coordination for synthesis from VHDL Ouaiss, Iyad |
| status_str | publishedVersion |
| title | A unified specification model of concurrency and coordination for synthesis from VHDL |
| title_full | A unified specification model of concurrency and coordination for synthesis from VHDL |
| title_fullStr | A unified specification model of concurrency and coordination for synthesis from VHDL |
| title_full_unstemmed | A unified specification model of concurrency and coordination for synthesis from VHDL |
| title_short | A unified specification model of concurrency and coordination for synthesis from VHDL |
| title_sort | A unified specification model of concurrency and coordination for synthesis from VHDL |
| url | http://hdl.handle.net/10725/5815 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php https://scholar.google.com/scholar?hl=en&q=A+unified+specification+model+of+concurrency+and+coordination+for+synthesis+from+VHDL&btnG=&as_sdt=1%2C5&as_sdtp= |