A unified specification model of concurrency and coordination for synthesis from VHDL
This paper proposes a Unified Specification Model (USM) of concurrency and coordination compatible with VHDL. The specification model embodies a uniform treatment of computation, communication channels, and memories, facilitating its use across a variety of synthesis applications. We briefly discuss...
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| Other Authors: | , , , |
| Format: | conferenceObject |
| Published: |
2017
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| Online Access: | http://hdl.handle.net/10725/5815 http://libraries.lau.edu.lb/research/laur/terms-of-use/articles.php https://scholar.google.com/scholar?hl=en&q=A+unified+specification+model+of+concurrency+and+coordination+for+synthesis+from+VHDL&btnG=&as_sdt=1%2C5&as_sdtp= |
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